
6. COMMUNICATION TIME
MELSEC-A
6-1
6. COMMUNICATION TIME
6.1
Transmission Delay Time When There is One Master Station
An explanation of the transmission delay time when there is one master station is given in the
following diagram. The following diagram (Fig. 6.1) shows an example for when there are 3 slave
stations.
Time
TO instruction FROM instruction
CPU module
Buffer memory
A1SJ71PB92D
Internal buffer
Slave1
Slave2
Slave3
Treq
(1)
Tres
(1)
Treq
(2)
Tres
(2)
Treq
(3)
Tres
(3)
Max_Tsdr
(1)
Max_Tsdr
(2)
Max_Tsdr
(3)
Lr
Pt
(1)
Pt
(2)
Pt
(3)
Tsdi
(M)
Tsdi
(M)
Tsdi
(M)
MSI(Min Slave Interval)
Bc
AJ71PB92D/
A1SJ71PB92D
AJ71PB92D/
Fig. 6.1
The transmission delay time when there is one master station