Mitsubishi Electric M32170F3VFP, Руководство пользователя

Страница: 822 / 850

21
21-16 Ver.0.10
PRELIMINARY PRELIMINARY
(4) Read and write timing
ELECTRICAL CHARACTERISTICS
21.5 AC Characteristics
t
c(BCLK)
BCLK Output Cycle Time
ns
16
BCLK Output High Pulse Width
t
w(BCLKH)
ns
17
tc(Xin)
2
t
w(BCLKL)
ns
18
tc(BCLK)
2
- 5
Address Delay Time after BCLK t
d(BCLKH-A)
ns
19
Chip Select Delay Time after BCLK
t
d(BCLKH-CS)
ns
20
Valid Address Time after BCLK
t
v(BCLKH-A)
ns
21
Valid Chip Select Time after BCLK
t
v(BCLKH-CS)
ns
22
Read Delay Time after BCLK
t
d(BCLKL-RDL)
ns
23
Valid Read Time after BCLK
t
v(BCLKH-RDL)
ns 24
Write Delay Time after BCLK
ns
25
Valid Write Time after BCLK
ns
26
Data Output Delay Time after BCLK
t
d(BCLKL-D)
ns
27
Valid Data Output Time after BCLK
t
v(BCLKH-D)
ns
28
Data Output Enable Time after BCLK
t
pzx(BCLKL-DZ)
ns
29
BCLK Output Low Pulse Width
Data Output Disable Time after BCLK
t
pxz(BCLKH-DZ)
ns
30
-11
-11
-12
-12
-16
-19
24
24
10
11
t
d(BCLKL-BLWL)
t
d(BCLKL-BHWL)
t
v(BCLKL-BHWL)
t
v(BCLKL-BLWL)
18
tc(BCLK)
2
- 5
5
See
Figure
21.5.6
21.5.7
21.5.8
Symbol Parameter
Rated Value
Unit
MIN MAX
Condition
t
d(A-RDL)
ns
39
Chip Select Delay Time before Read
t
d(CS-RDL)
ns 40
Valid Address Time after Read
t
v(RDH-A)
41
ns
0
tc(BCLK)
2
-15
Valid Chip Select Time after Read
t
v(RDH-CS)
42
ns
0
Data Output Enable Time after Read t
pzx(RDH-DZ)
46
ns
tc(BCLK)
2
-15
tc(BCLK)
2
Address Delay Time before Read
t
d(A-BLWL)
Address Delay Time before Write
(Byte write mode)
ns
47
Chip Select Delay Time before Write
(Byte write mode)
ns 48
Valid Address Time after Write
(Byte write mode)
49 ns
tc(BCLK)
2
-15
Valid Chip Select Time after Write
(Byte write mode)
50 ns
tc(BCLK)
2
-15
t
d(A-BHWL)
t
d(CS-BLWL)
t
d(CS-BHWL)
t
v(BLWH-A)
t
v(BHWH-A)
t
v(BLWH-CS)
t
v(BHWH-CS)
tc(BCLK)
2
-15
tc(BCLK)
2
-15