Mitsubishi Electric M32170F3VFP, Руководство пользователя

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21
21-14 Ver.0.10
PRELIMINARY PRELIMINARY
(7) Input transition time on JTAG pin
Note: Stipulated values are guaranteed values when the test pin load capacitance CL=80pF.
(8) JTAG interface timing
t
c(JTCK)
JTCK Input Cycle Time
ns
JTCK Input High Pulse Width
t
w(JTCKH)
ns 61
t
w(JTCKL)
ns
62
JTDI, JTMS Input Setup Time
t
su(JTDI-JTCK)
ns
63
JTDI, JTMS Input Hold Time
t
h(JTCK-JTDI)
ns 64
ns
65
66
JTCK Input Low Pulse Width
ns
67
t
d(JTCK-JTDOV)
t
d(JTCK-JTDOX)
t
W(JTRST)
JTDO Output Delay Time after JTCK Fall
JTDO Output Hi-Z Delay Time after JTCK Fall
TRST Input Low Pulse Width
100
40
40
15
20
40
40
60
tc(JTCK)
ns
See
Figure
21.5.11
Symbol
Rated Value
Unit
MIN MAX
Condition
t
r
ns
58
ns
Input Rising
Transition Time
t
f
ns
ns
59
Input Falling
Transition Time
Other than JTRST pin
JTRST pin
Other than JTRST pin
JTRST pin
(JTCK,JTDI,JTMS,JTDO)
When using
TAP
When not using
TAP
(JTCK,JTDI,JTMS,JTDO)
10
10
2
10
10
2
ms
ms
See
Figure
21.5.10
Symbol
Rated Value
Unit
MIN MAX
Condition
When using
TAP
When not using
TAP
(6) Bus arbitration timing
ELECTRICAL CHARACTERISTICS
21.5 AC Characteristics
t
su(HREQL-BCLKH)
HREQ Input Setup Time before BCLK
ns
35
HREQ Input Hold Time after BCLK t
h(BCLKH-HREQL)
27
0 ns
36
See
Figure
21.5.9
Symbol Parameter
Rated Value
Unit
MIN MAX
Condition
Note: Stipulated values are guaranteed values when the test pin load capacitance CL=80pF.