MiTAC MiNote 7321, Руководство по обслуживанию

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7321 N/B Maintenance 7321 N/B Maintenance
5.2 VIA VT8362 North Bridge with S3 Savage4 AGPX4
Miscellaneous Functions
Signal Name PIN # I/O Signal Description
XIN E1 I Reference Frequency Input. An external 14.318 MHz crystal is
connected between XOUT and this pin. Alternatively, an external
oscillator can be connected.
XOUT E2 O Crystal Output. This pin drives the crystal via an internal
oscillator. If an external oscillator is connected to XIN, this pin
can be left unconnected.
SPCLK[2:1] M2, AE5 IO Serial Port Clocks. These are the clocks for serial data transfer.
SPCLK1 is typically used for I²C communications. As an output,
it is programmed via CRA0[0]. As an input, its status is read via
CRA0[2]. In either case the serial port must be enabled by
CRA0[4] = 1. SPCLK2 is typically used for DDC monitor
communications. As an output, it is programmed via CRB1[0]. As
an input, its status is read via CRB1[2]. The port is enabled via
CRB1[4] = 1.
SPDAT[2:1] M3, AD5 IO Serial Port Data. These are the data signals used for serial data
transfer. SPDAT1 is typically used for I²C communications. As an
output, it is programmed via CRA0[1]. As an input, its status is
read via CRA0[3]. In either case the serial port must be enabled
by CRA0[4] = 1. SPDAT2 is typically used for DDC monitor
communications. As an output, it is programmed via CRB1[1]. As
an input, its status is read via CRB1[3]. The port is enabled via
CRB1[4] = 1.
STRW /
GPOUT AE2 O General Purpose Output. This pin reflects the state of SRD[0].
GOP0 AF2 O General Output Port. When SR1A[4] is cleared, this pin reflects
the state of CR5C[0].
STPAGP# AE3 I Stop AGP. Power management for internal AGP.
AGPBUSY# AD4 I/O AGP Busy. Power management for internal AGP.
STANDBY AE4 I Standby. Used to put the integrated graphics controller in the
standby state.
SUSPEND AC5 I Suspend. Used to put the integrated graphics controller in the
suspend state.
SUSST# AB19 I Suspend Status. For implementation of the Suspend-to-DRAM
feature. Connect to an external pullup to disable.
ZV-Port Interface
Signal Name PIN # I/O Signal Description
ZVD[15:0] (see pin table) I ZV-Port Data Bus Video Input.
ZVHS V3 I ZV-Port Horizontal Sync.
ZVVS V1 I ZV-Port Vertical Sync.
ZVCLK
W3 I
ZV-Port Clock.
Clock / Reset Control
Signal Name PIN # I/O Signal Description
HCLK G22 I Host Clock. This pin receives the host CPU clock (66 / 100 / 133
MHz). This clock is used by all TwisterK logic that is in the host
CPU domain.
PCLK
AB18 I
PCI Clock.
This pin receives a buffered host clock divided-by-3 to
create 33 MHz. This clock is used by all of the TwisterK logic that
is in the PCI clock domain. This clock input must be 33 MHz
maximum to comply with PCI specification requirements and must
be synchronous with the host CPU clock, HCLK, with an
HCLK:PCLK frequency ratio of 3:1. The host CPU clock must lead
the PCI clock by 2.0 ± 1.0 nsec.
MCLK R22 O DRAM Clock. Output from internal clock generator to the external
clock buffer.
MCLKF P23 I DRAM Clock Feedback. Input from the external clock buffer.
RESET# AD18 I Reset. Input from South Bridge chip. When asserted, this signal
resets TwisterK and sets all register bits to the default value. The
rising edge of this signal is used to sample all power-up strap
options
PWROK AC19 I Power OK. Connect to South Bridge and Power Good circuitry.
5. Pin Descriptions of Major Components