MiTAC MiNote 7321, Руководство по обслуживанию

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7321 N/B Maintenance 7321 N/B Maintenance
5.4 PC Card Interface controller
16-Bit PC Card Interface Control (Slots A and B)
TERMINAL
NO.
SLOT A† SLOT B‡
NAME
PDV GHK PDV GHK
I/O DESCRIPTION
WE 110 R19 46 P3 O Write enable. WE is used to strobe memory write
data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ
programmable memory technologies.
DMA terminal count. WE is used as TC during
DMA operations to a 16-bit PC Card that
supports DMA. The PCI1420 asserts WE to
indicate TC for a DMA read operation.
WP(IOIS16) 139 H18 73 U9 I Write protect. WP applies to 16-bit memory PC
Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit
I/O cards, WP is used for the 16-bit port
(IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC
Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an
address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of
16-bit accesses.
DMA request. WP can be used as the DMA
request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, then the PC
Card asserts WP to indicate a request for a DMA
operation.
VS1
VS2 134
122 J18
M19
68
56 U8
P7
I/O Voltage sense 1 and voltage sense 2. VS1 and
VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
† Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19
are A_WE.
‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3
are B_WE.
CardBus PC Card Interface System (Slots A and B)
TERMINAL
NO.
SLOT A† SLOT B‡
NAME
PDV GHK PDV GHK
I/O DESCRIPTION
CCLK 112 P18 48 P6 O CardBus clock. CCLK provides synchronous
timing for all transactions on the CardBus
interface. All signals except CRST, CCLKRUN,
CINT, CSTSCHG, CAUDIO, CCD2, CCD1,
CVS2, and CVS1 are sampled on the rising edge
of CCLK, and all timing parameters are defined
with the rising edge of this signal. CCLK
operates at the PCI bus clock frequency, but it
can be stopped in the low state or slowed down
for power savings.
CCLKRUN 139 H18 73 U9 O CardBus clock run. CCLKRUN is used by a
CardBus PC Card to request an increase in the
CCLK frequency, and by the PCI1420 to indicate
that the CCLK frequency is going to be
decreased.
CRST 124 L18 58 W5 I/O CardBus reset. CRST brings CardBus PC
Card-specific registers, sequencers, and signals
to a known state. When CRST is asserted, all
CardBus PC Card signals are placed in a
high-impedance state, and the PCI1420 drives
these signals to a valid logic level. Assertion can
be asynchronous to CCLK, but deassertion must
be synchronous to CCLK.
† Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18
are A_CCLK.
‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6
are B_CCLK.
5. Pin Descriptions of Major Components