MiTAC MiNote 7321, Руководство по обслуживанию

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M/B Layout Arrangement
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Revision Description
MODEL : 7321 M/B
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Content
ISSUES
13
DRAWN
11
Page
1) Initial schematics release.
Revision : 0B
07
Table of Content
CHECK
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Page Setting & Revision History
Revision History
PCI Devices Resources
04
01/19/2001 00 01
DESIGN
Date
15
16
17
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Block Diagram
CPU-K7 (1/2)
CPU-K7 (2/2)
Twister-K (1/2)
Twister-K (2/2) & TV Encoder
SO-DIMM Socket
On Board SDRAM
SB-VT8231(1/3) PCI, I/O, FDD
SB-VT8231(2/3) IDE, CPU, AC97
SB-VT8231(3/3) MII, ISA
Unused Part & Screw Hole
Cardbus Controller (PCI1420)
PCMCIA Socket
1394 (NEC uPD72872)
LAN-PHY (LSI 80227), MDC
Display Interface
Clock Generator (ICS9248-193)
AC97 Codec
Audio AMP
SIO, PIO, FIR
HDD, FDD, CDROM Connector
Enbedded Controller (H8)
USB, Inverter, Touchpad Connector
System BIOS, Charger BD, QSB, LED Connector
D/D Interface, VID, FID
VDD5, RTC Battery, Thermo Sensor
CPUCORE Power
+3V/+5V/+12V Power
Charger
ADINP & Discharger
19
20
21
22
23
24
25
26
27
28
29
30
31
Component Layer
Ground Plane Ground Layer
Inner 1 Layer
Inner 2 Layer
Power Layer Power Plane
Solder Layer
Normal Trace Width - Space: 5 - 6
Trace Impedence: 60 ohm
Cardbus
IDSEL
(REQ# & GNT#)
Bus Master INT#
AD19 0 INTB#
1394 AD22 3 INTC#
LAN
AUDIO
USB
D18, F0
D17, F5,6
D17, F2
4 (High)
VDD5:
CPU, VT8362
H8, IMP811, AME8800 (U511)
+5V:
Card Power Switch, ADP3301, LCD panel MOS, H8 12V
74VHC164, LED, LMV393, MAX4173F
Power Plane
VDD3:
+CPU_CORE:
CH7005C, MDC, Audio Codec, PIO, HDD, CDROM,
FDD, CBTD3384, FAN, SYS BIOS, LED
LP2951
VT8362, VT8362 (VGA, DAC, PLL...), CPU_VCCA
VDD5S:
VT8231 Resume Well, RTC, VT8321 MII
+VMAIN:
+3V:
+12V:
+2.5V:
+2.5V (PQ13), AME8800 (U505), VT8362, VT8231, 1394, LCD
Panel, EEPROM, Clock Generator, RS232, FIR, ADM1022,
ADM809, Codec (Digital), 244 Buffer
0A 1) Change LAN PHY from ICS1893 to LSI80227.
2) Correct the LVDS PLL power from +3V to +2.5V.
3) GPI0, GPI8 pull high from +VCC_RTC to +VDD3.
4) SMBUS pull high from resistor array to single resistor.
5) Correct internal keyboard matrix from connector.
6) Correct the PS/2 connector shape.
7) Correct internal MIC connector shape.
8) Change cardbus controller GRST# from RC reset to PCIRST#.
9) Change Q502 power on signal from +5V to +3.3V.
10) Change Q20, Q505 from DTC144TKA to MMBT3904 with a
1.5K resistor.
11) Correct CKE pin arrangement from chipset side.
12) Fix cardbus controller pull high arrangement (RP504,505).
13) Change QSB keyboard matrix arrangement.
N.B.
S.B.
DEVICE
D0, D1
D17
D8
D11
14) Change Line in Cap. from 1U to 4.7U.
15) Change DDCK, DDDA pull up from +5V to +3V.
16) Add 5 capcitators at screw hole, for EMI.
17) Add a extra 4.7 ohm with a 4.7U for AMP 5V.
03/21/2001
18) Add H8_RSMRST at P95, change GREEN_LIGHT to PA2,
and delete IQSB1#.
19) Reserve VGA_SUS pull-low.
1) Resume on 6/8.
2) Phase in STR schematics.
3) Phase in 2 phase CPU power swtiching circuit (LTC1709EG-7).
VDD5 Switch Circuit (Q22), AMP, USB, Card Power Switch, Touchpad +5V_STR:
AME8800 (U517), Memory, VT8231 USB Interface, U512, MDC,
LAN-PHY, Card Power Switch, RS-232, Cardbus Controller
+3V_STR:
VT8362 Resume Well +2.5V_STR:
4) Change Panel ID to VGA Strapping.
5) Change VT8321 & H8 GPIO to follow other model design.
6) Change PowerOK timing for CPU_PWRGOOD faster than
SYS_PWRGOOD.
0B 07/02/2001
<Doc>
0B
7321 M/B schematics
C
1 31 Monday, July 02, 2001
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