MiTAC MiNote 7321, Руководство по обслуживанию

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7321 N/B Maintenance 7321 N/B Maintenance
5.2 VIA VT8362 North Bridge with S3 Savage4 AGPX4
DRAM Interface
Signal Name PIN # I/O Signal Description
MD[63:0] (see pinout tables) IO Memory Data. These signals are connected to the DRAM
data bus. Output drive strength may be set by Device 0
Rx6D[4].
MA14 / strap,
MA13 / strap,
MA12 / strap,
MA11 / strap,
MA10 / strap,
MA9 / strap,
MA8 / strap,
MA7 / strap,
MA6 / strap,
MA5 / strap,
MA4 / strap,
MA3 / strap,
MA2 / strap,
MA1 / strap,
MA0 / strap
W22
W23
W24
W25
W26
V24
V25
U21
V22
U22
V23
T22
V26
U23
U24
O/ I Memory Address. DRAM address lines
St r ap
St r ap St r ap
St r ap Re gi s t e r
Re gi s t e r Re gi s t e r
Re gi s t e r De s c r i pt i on
De s c r i pt i on De s c r i pt i on
De s c r i pt i on Se t t i ngs
Se t t i ngs Se t t i ngs
Se t t i ngs
MA 1 4 Rx68[ 0] CPU Cl ock Fr equency 0= 1 00, 1 = 1 33
MA 1 3- 1 2 RxB4[ 7- 6] Dr i ve St r engt h f or Ri s e 11 =Aut o, ~ 11 =St r ap
MA 11 RxB6[ 7] S2K Edge/ Cent r al DQ 0=Cent r al , 1 =Edge
MA 1 0- 9 RxB4[ 3- 2] Dr i ve St r engt h f or Fal l 0=Aut o, ~0=St r ap
MA8- 4 RxB6[ 5- 1 ] S2K St r obe Del ay 0=Aut o, ~0=St r ap
MA3- 0 RxB3[ 6- 3] CPU Cl ock Di vi de 0= 11 , 1 = 11 . 5, 2= 1 2,
3= 1 2. 5, 4=5, 5=5. 5,
6=6, 7=6. 5, 8=7, 9=7. 5,
1 0=8, 11 =8. 5, 1 2=9,
1 3=9. 5, 1 4= 1 0, 1 5= 1 0. 5
SRASA# RxB2[ 5] S2K Sl ew Rat e Cont r ol 0=Enabl e, 1 =Di s abl e
SCASA# RxB3[ 1 ] Fas t Command 0=Di s abl e, 1 =Enabl e
SWEA# RxB6[ 6] CPU Edge/ Cent er DQ 0=Edge, 1 =Cent er
Strap option default values are all 0 (internally pulled
down) MA output drive strength may be set by Device 0
Rx6C[7] and 6D[2]. Cmd output drive strength may be set
by Device 0 Rx6C[6] and 6D[3].
CS[5:0]# Y23, Y22, AA25,
AA26, Y26, Y25
O Chip Select. Chip select of each bank. Output drive
strength may be set by Device 0 Rx6D[0].
DQM[7:0] R24, T26, AA24,
AB26, R26, R23,
AA22, AA23
O Data Mask. Data mask of each byte lane. Output drive
strength may be set by Device 0 Rx6D[1].
SRASA# /
strap
U25 O Row Address Command Indicator. (strap at Device 0
RxB2[5])
SCASA# /
strap
P25 O Column Address Command Indicator. (strap at Device
0 RxB3[1])
SWEA# /
strap
AB24 O Write Enable Command Indicator. (strap at Device 0
RxB6[6])
CKE0 /
SWEC#,
CKE1 /
SCASC#,
CKE2 /
SWEB#,
CKE3 /
SCASB#,
CKE4 /
SRASC#,
CKE5 /
SRASB#
U26
T25
P26
R25
AC26
AB25
O Clock Enables. Clock enables for each DRAM bank for
powering down the SDRAM or clock control for reducing
power usage and for reducing heat / temperature in
high-speed memory systems. See Device 0 Rx78[0] and
RxE0[4].
PCI Bus Interface
Signal Name PIN # I/O Signal Description
AD[31:0] (see pinout tables) IO Address/Data Bus. The standard PCI address and data
lines. The address is driven with FRAME# assertion and
data is driven or received in following cycles.
CBE[3:0]# AC10, AB12,
AF14, AE15
IO Command/Byte Enable. Commands are driven with
FRAME# assertion. Byte enables corresponding to
supplied or requested data are driven on following clocks.
FRAME# AC12 IO Frame. Assertion indicates the address phase of a PCI
transfer. Negation indicates that one more data transfer is
desired by the cycle initiator.
IRDY# AF12 IO Initiator Ready. Asserted when the initiator is ready for
data transfer.
TRDY# AE12 IO Target Ready. Asserted when the target is ready for data
transfer.
STOP#
AB13 IO
Stop.
Asserted by the target to request the master to stop
the current transaction.
DEVSEL# AD12 IO Device Select. This signal is driven by the VT8362 when a
PCI initiator is attempting to access main memory. It is an
input when the VT8362 is acting as a PCI initiator.
PAR
AE13 IO
Parity.
A single parity bit is provided over AD[31:0] and
C/BE[3:0].
SERR# AF13 IO System Error. The VT8362 will pulse this signal when it
detects a system error condition.
LOCK# AC13 IO Lock. Used to establish, maintain, and release resource
lock.
PREQ# AE18 I South Bridge Request. This signal comes from the South
Bridge. PREQ# is the South Bridge request for the PCI
bus.
PGNT# AF18 O South Bridge Grant. This signal driven by the VT8362 to
grant PCI access to the South Bridge.
REQ[4:0]# AB8, AC6, AC7,
AE6, AE7
I PCI Master Request. PCI master requests for PCI.
GNT[4:0]#
AB7, AD6, AD7,
AF6, AF7
O
PCI Master Grant.
Permission is given to the master to
use PCI.
PCLK AB18 I PCI Clock. From external clock generator.
PCKRUN# AC17 IO PCI Clock Run. May be used to stop PCI clock.
INTA#
AB6 O
PCI Interrupt Out.
An asynchronous active low output
used to signal an event that requires handling on behalf of
the internal integrated graphics controller. If MA2 is
strapped high at reset (clearing CR36[0]) no interrupt will
be requested during PCI configuration. The default drive
strength is 24 mA (other drive strengths may be selected
via CR80[1-0]).
5. Pin Descriptions of Major Components