MiTAC MiNote 7321, Руководство по обслуживанию

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7321 N/B Maintenance 7321 N/B Maintenance
5.2 VIA VT8362 North Bridge with S3 Savage4 AGPX4
PCI Bus Interface
Signal Name PIN # I/O Signal Description
WSC# AC18 O Write Snoop Complete. Sideband PCI signal (used on the
planar only in multiprocessor configurations) asserted to
indicate that all snoop activity on the CPU bus initiated by
the last PCI-to-DRAM write is complete and that it is safe
to send an APIC interrupt message. Basically this signal is
always active except when PCI master write data is not
flushed.
LCD Panel Interface
Signal Name PIN # I/O Signal Description
FPD[35:0] (see pin table) O Panel Data. Internally pulled down during reset. 8mA is the
default. 16mA is selected via SR3D[6]=1.
FPDET AA7 I Panel Detect. If SR30[1]=0, SR30[2] will read 1 if a Flat
Panel is appropriately connected. Must be tied to GND if not
used.
FPVS
G3 O
Panel VSYNC.
Internally pulled down.
FPHS G5 O Panel HSYNC. Internally pulled down.
FPDE H3 O Panel Data Enable. Internally pulled down.
FPCLK G4 O Panel Clock. Internally pulled down during reset. 8mA is
the default. 16mA may also be selected.
FPGPIO G1 I/O General Purpose Input/Output.
ENVDD
F1 O
Enable VDD.
This signal is driven high to external logic to
initiate a flat panel power up sequence.
ENVEE H5 O Enable VEE. This signal is driven high to a programmable
time after ENVDD is driven high during a flat panel power
up sequence.
Flat Panel Monitor (DVI) Interface
Signal Name PIN # I/O Signal Description
FPD[11:0] (see pin table) O Panel Data. Internally pulled down during reset. 8mA is the
default. 16mA is selected via SR3D[6]=1. This function is
selected on these pins when SR31[4] = 1.
FPDET AA7 I Panel Detect. If SR30[1]=0, SR30[2] will read 1 if a Flat
Panel is appropriately connected. Must be tied to GND if not
used.
FPVS G3 O Panel VSYNC. Internally pulled down.
FPHS G5 O Panel HSYNC. Internally pulled down.
FPDE H3 O Panel Data Enable. Internally pulled down.
FPCLK G4 O Panel Clock. Internally pulled down during reset. 8mA is
the default. 16mA may also be selected.
CRT Interface
Signal Name PIN # I/O Signal Description
RSET C1 A Reference Resistor. Tie to GNDRGB through an external
140??resistor to control
the RAMDAC full-scale current value.
AR C2 A Analog Red. Analog red output to the CRT monitor.
AB B2 A Analog Blue. Analog blue output to the CRT monitor.
AG B1 A Analog Green. Analog green output to the CRT monitor.
HSYNC F5 O Horizontal Sync. Output to CRT.
VSYNC F4 O Vertical Sync. Output to CRT.
TV Encoder Interface
Signal Name PIN # I/O Signal Description
TVD[11:0] (see pin table) O TV Data. Internally pulled down during reset
TVCLK
/
FPD32
N5 I
TV Clock.
Input clock from encoder. Internally pulled
down.
TVCLKR /
FPD16
K5 O TV Return Clock. Output clock to TV encoder. Internally
pulled down.
TVVS /
FPD31
R4 O TV VSYNC. Internally pulled down during reset
TVHS /
FPD34
R5 O TV HSYNC. Internally pulled down during reset
TVBL#
/
FPD17
L1 O
TV Blanking.
Internally pulled down during reset
LVDS Interface
Signal Name PIN # I/O Signal Description
Y[2:0]P
Y[2:0]M
AC2, AD3, AD1
AC1, AD2, AD4 A
A
LVDS Data Positive Output.
LVDS Data Negative Output.
YCP
YCM
AB4
AA5 A
A LVDS Clock Positive Output.
LVDS Clock Negative Output.
Z[2:0]P
Z[2:0]M AA4, AB2, AB3
A3, AB1, AC3
A
A
2 nd LVDS Data Positive Output.
2 nd LVDS Data Negative Output.
ZCP
ZCM
AA1
AA2 A
A
2 nd LVDS Clock Positive Output.
2 nd LVDS Clock Negative Output.
5. Pin Descriptions of Major Components