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Hub Interface Signals
Signal Name
Type
Description
HI[11:0]
I/O
Hub Interface Signals
HI_STB/HI_STBS
I/O
Hub Interface Strobe/ Hub Interface Strobe Second:
One of two
differential strobe signals used to transmit and receive data through
the hub interface.
Hub Interface 1.5 mode this signal is not differential and is the
second of the two strobe signals.
HI_STB#/
HI_STBF
I/O
Hub Interface Strobe Complement / Hub Interface Strobe First:
One of two differential strobe signals used to transmit and receive
data through the hub interface.
Hub Interface 1.5 mode this signal is not differential and is the first
of the two strobe signals.
HICOMP
I/O
Hub Interface Compensation:
Used for hub interface buffer
compensation.
HI_VSWING
I
Hub Interface Voltage Swing:
Analog input used to control the
voltage swing and impedance strength of hub interface pins.
LAN Connect Interface Signals
Signal Name
Type
Description
LAN_CLK
I
LAN I/F Clock:
Driven by the LAN Connect component.
Frequency range is 5 MHz to 50 MHz.
LAN_RXD[2:0]
I
Received Data:
The LAN Connect component uses these signals to
transfer data and control information to the integrated LAN
Controller. These signals have integrated weak pull-up resistors.
LAN_TXD[2:0]
O
Transmit Dat
a: The integrated LAN Controller uses these signals
to transfer data and control information to the LAN Connect
component.
LAN_RSTSYNC
O
LAN Reset/Sync:
The LAN Connect component’s Reset and Sync
signals are multiplexed onto this pin.
EEPROM Interface Signals
Signal Name
Type
Description
EE_SHCLK
O
EEPROM Shift Cloc
k: Serial shift clock output to the EEPROM.
EE_DIN
I
EEPROM Data I
n: Transfers data from the EEPROM to the ICH3.
This signal has an integrated pull-up resistor.
EE_DOUT
O
EEPROM Data Ou
t: Transfers data from the ICH3 to the
EEPROM.
EE_CS
O
EEPROM Chip Selec
t: Chip select signal to the EEPROM.
Firmware Hub Interface Signals
Signal Name
Type
Description
FWH[3:0]/
LAD[3:0]
I/O
Firmware Hub Signals.
Muxed with LPC address signals.
FWH[4]/
LFRAME#
I/O LFRAME#
Firmware Hub Signals.
Muxed with LPC LFRAME#
signal.
PCI Interface Signals
Signal Name
Type
Description
AD[31:0]
I/O
PCI Address/Data:
AD[31:0] is a multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a
physical address (32 bits). During subsequent clocks, AD[31:0]
contain data. The ICH4 drives all 0s on AD[31:0] during the address
phase of all PCI Special Cycles.
C/BE[3:0]#
I/O
Bus Command and Byte Enables:
The command and byte enable
signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3:0]# define the bus command. During
the data phase, C/BE[3:0]# define the Byte Enables.
C/BE[3:0]# Command Type
0 0 0 0 Interrupt Acknowledge
0 0 0 1 Special Cycle
0 0 1 0 I/O Read
0 0 1 1 I/O Write
0 1 1 0 Memory Read
0 1 1 1 Memory Write
1 0 1 0 Configuration Read
1 0 1 1 Configuration Write
1 1 0 0 Memory Read Multiple
1 1 1 0 Memory Read Line
1 1 1 1 Memory Write and Invalidate
All command encodings not shown are reserved. The ICH4 does not
decode reserved values, and therefore will not respond if a PCI
master generates a cycle using one of the reserved values.
DEVSEL#
I/O
Device Select:
The ICH4 asserts DEVSEL# to claim a PCI
transaction. As an output, the ICH4 asserts DEVSEL# when a PCI
master peripheral attempts an access to an internal ICH4 address or
an address destined for the hub interface (main memory or AGP).
As an input, DEVSEL# indicates the response to an ICH4-initiated
transaction on the PCI bus. DEVSEL# is tri-stated from the leading
edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until
driven by a Target device.
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(1)
MiTac Secret
Confidential Document
