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AGP Strobe Descriptions
Signal Name
Type
Description
GADSTB[0]
I/O
AGP
Address/Data Bus Strobe-0:
provides timing for 2x and 4x data on
AD[15:0]
and
C/BE[1:0]#
signals. The agent that is providing the
data will drive this signal.
GADSTB#[0]
I/O
AGP
Address/Data Bus Strobe-0 Complement:
With AD STB0, forms a
differential strobe pair that provides timing information for the
AD[15:0]
and
C/BE[1:0]#
signals. The agent that is providing the
data will drive this signal.
GADSTB[1]
I/O
AGP
Address/Data Bus Strobe-1:
Provides timing for 2x and 4x data on
AD[31:16]
and
C/BE[3:2]#
signals. The agent that is providing the
data will drive this signal.
GADSTB#[1]
I/O
AGP
Address/Data Bus Strobe-1 Complement:
With AD STB1, forms a
differential strobe pair that provides timing information for the
AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is
providing the data will drive this signal.
GSBSTB
I
AGP
Sideband Strobe:
Provides timing for 2x and 4x data on the
SBA[7:0]
bus. It is driven by the AGP master after the system has
been configured for 2x or 4x sideband address mode.
GSBSTB#
I
AGP
Sideband Strobe Complement:
The differential complement to the
SB_STB
signal. It is used to provide timing 4x mode.
AGP/PCI Signals-Semantics Descriptions
Signal Name
Type
Description
GFRAME#
I/O
AGP
G_FRAME:
Frame.
During PIPE# and SBA Operation:
Not used by AGP SBA and
PIPE# operations.
During Fast Write Operation:
Used to frame transactions as an
output during Fast Writes.
During FRAME# Operation:
G_FRAME# is an output when the
GMCH acts as an initiator on the AGP Interface. G_FRAME# is
asserted by the GMCH to indicate the
beginning and duration of an access. G_FRAME# is an input when
the GMCH acts as a FRAME#-based AGP target. As a
FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and
the AD[31:0] signals on the first clock edge on which
GMCH samples FRAME# active.
GIRDY#
I/O
AGP
G_IRDY#: Initiator Ready.
During PIPE# and SBA Operation:
Not used while enqueueing
requests via AGP SBA and PIPE#, but used during the data phase of
PIPE# and SBA transactions.
During FRAME# Operation:
G_IRDY# is an output when GMCH
acts as a FRAME#-based AGP initiator and an input when the GMCH
acts as a FRAME#-based AGP target. The assertion of G_IRDY#
indicates the current FRAME#-based AGP bus initiator's ability to
complete the current data phase of the transaction.
During Fast Write Operation:
In Fast Write mode, G_IRDY#
indicates that the AGP-compliant master is ready to provide all write
data for the current transaction. Once G_IRDY# is asserted for a write
operation, the master is not allowed to insert wait states. The master is
never allowed to insert a wait state during the initial data transfer (32
bytes) of a write transaction. However, it may insert wait states after
each 32-byte block is transferred.
5.2 Intel 855GM/GME North Bridge(5)
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