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Power Management Interface Signals
Signal Name
Type
Description
THRM#
I
Thermal Alarm:
This is an active low signal generated by external
hardware to start the hardware clock throttling mode. The signal can
also generate an SMI# or an SCI.
THRMTRIP#
I
Thermal Trip:
When low, THRMTRIP# indicates that a thermal
trip from the processor occurred; the ICH4 will immediately
transition to a S5 state. The ICH4 will not wait for the processor
stop grant cycle since the processor has overheated.
SLP_S1#
O
S1 Sleep Control:
SLP_S1# provides Clock Synthesizer or Power
plane control. Optional use is to shut off power to non-critical
systems when in the S1- M (Powered On Suspend), S3 (Suspend To
RAM), S4 (Suspend to Disk) or S5 (Soft Off) states.
SLP_S3#
O
S3 Sleep Control:
SLP_S3# is for power plane control. It shuts off
power to all non-critical systems when in S3 (Suspend To RAM),
S4 (Suspend to Disk), or S5 (Soft Off) states.
SLP_S4#
O
S4 Sleep Control:
SLP_S4# is for power plane control. It shuts
power to all non-critical systems when in the S4 (Suspend to Disk)
or S5 (Soft Off) state.
SLP_S5#
O
S5 Sleep Control:
SLP_S5# is for power plane control. The signal
is used to shut power off to all non-critical systems when in the S5
(Soft Off) states.
PWROK
I
Power OK:
When asserted, PWROK is an indication to the ICH4
that core power and PCICLK have been stable for at least 1 ms.
PWROK can be driven asynchronously. When PWROK is negated,
the ICH4 asserts PCIRST#.
NOTE:
PWROK must deassert for a minimum of 3 RTC clock
periods for the ICH4 to fully reset the power and properly generate
the PCIRST# output
PWRBTN#
I
Power Button:
The Power Button causes SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal causes a wake event. If PWRBTN# is pressed
for more than 4 seconds, this causes an unconditional transition
(power button override) to the S5 state with only the PWRBTN#
available as a wake event. Override occurs even if the system is in
the S1-M–S4 states. This signal has an internal pull-up resistor.
RI#
I
Ring Indicate:
This signal is an input from the modem interface. It
can be enabled as a wake event, and this is preserved across power
failures.
SYS_RESET#
I
System Reset:
This pin forces an internal reset after being
debounced. The ICH4 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle
before forcing a reset on the system.
RSMRST#
I
Resume Well Reset:
This signal is used for resetting the resume
power plane logic.
Power Management Interface Signals (Continued)
Signal Name
Type
Description
LAN_RST#
I
LAN Reset:
This signal must be asserted at least 10 ms after the
resume well power (VccLAN3_3 and VccLAN1_5 is valid. When
deasserted, this signal is an indication that the resume well power is
stable.
SUS_STAT#/
LPCPD#
O
Suspend Status:
This signal is asserted by the ICH4 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs
that may be going to powered-off planes. This signal is called
LPCPD# on the LPC I/F.
C3_STAT#
O
C3_STAT#:
This signal will typically be configured as C3_STAT#.
It is used for indicating to an AGP device that a C3 state transition
is beginning or ending. If C3_STAT# functionality is not required,
this signal may be used as a GPO.
NOTE:
This signal will be asserted in S1-M on the ICH4-M.
SUSCLK
O
Suspend Clock:
Output of the RTC generator circuit to use by other
chips for refresh clock.
AGPBUSY#
I
AGP Bus Busy:
To support the C3 state. This signal is an
indication that the AGP device is busy. When this signal is asserted,
the BM_STS bit will be set. If this functionality is not needed, this
signal may be configured as a GPI.
STP_PCI#
O
Stop PCI Clock:
This signal is an output to the external clock
generator for it to turn off the PCI clock. Used to support PCI
CLKRUN# protocol. If this functionality is not needed, This signal
can be configured as a GPO.
STP_CPU#
O
Stop CPU Clock:
Output to the external clock generator for it to
turn off the processor clock. Used to support the C3 state. If this
functionality is not needed, this signal can be configured as a GPO.
BATLOW#
I
Battery Low:
This signal is an input from the battery to indicate
that there is insufficient power to boot the system. Assertion will
prevent wake from S1-M–S5 state. Can also be enabled to cause an
SMI# when asserted.
CPUPERF#
OD
CPU Performance:
CPUPERF# is used for Intel SpeedStep
technology support. The signal selects which power state to put the
processor in.
SSMUXSEL
O
SpeedStep Mux Select:
SSMUXSEL is used for Intel SpeedStep
technology support. The signal selects the voltage level for the
processor.
VGATE/
VRMPWRGD
I
VGATE/VRM Power Good:
VGATE/VRMPWRGD is used for
Intel SpeedStep technology support. This is an output from the
processor’s voltage regulator to indicate that the voltage is stable.
This signal may go inactive during an Intel SpeedStep transition.
5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(5)
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