8050
8050
D N/B Maintenance
D N/B Maintenance
83
GPIO Signal Descriptions
GPIO I/F Total
Type
Comments
RSTIN#
I
CMOS
Reset:
Primary Reset, Connected to PCIRST# of ICH4-M.
PWROK
I
CMOS
Power O
K: Indicates that power to GMCH is stable.
AGPBUSY#
O
CMOS
AGPBUSY:
Output of the GMCH IGD to the ICH4-M, which
indicates that certain graphics activity is taking place. It will indicate
to the ACPI software not to enter the C3 state. It will
also cause a C3/C4 exit if C3/C4 was being entered, or was already
entered when
AGPBUSY# went active. Not active when the IGD is in any ACPI
state other than D0.
EXTTS_0
I
CMOS
External Thermal Sensor Input:
This signal is an active low input
to the GMCH and is used to monitor the thermal condition around the
system memory and is used for triggering a read throttle. The GMCH
can be optionally programmed to send a SERR, SCI, or SMI message
to the ICH4-M upon the triggering
of this signal.
LCLKCTLA
O
CMOS
SSC Chip Clock Control:
Can be used to control an external clock
chip with SSC control.
LCLKCTLB
O
CMOS
SSC Chip Data Control:
Can be used to control an external clock
chip for SSC control.
PANELVDDEN
O
CMOS
LVDS LCD Flat Panel Power Control:
This signal is used enable
power to the panel interface.
PANELBKLTE
N
O
CMOS
LVDS LCD Flat Panel Backlight Enable:
This signal is used to
enable the backlight inverter (BLI)
PANELBKLTC
TL
O
CMOS
LVDS LCD Flat Panel Backlight Brightness Control:
This signal
is used as the Pulse
Width Modulated (PWM) control signal to control the backlight
inverter.
DDCACLK
I/O
CMOS
CRT DDC Clock:
This signal is used as the DDC clock signal
between the CRT monitor and the GMCH.
DDCADATA
I/O
CMOS
CRT DDC Data:
This signal is used as the DDC data signal between
the CRT monitor and the GMCH.
DDCPCLK
I/O
CMOS
Panel DDC Clock:
This signal is used as the DDC clock signal
between the LFP and the GMCH.
DDCPDATA
I/O
CMOS
Panel DDC Data:
This signal is used as the DDC data signal
between the LFP and the GMCH.
GPIO I/F Total
Type
Comments
MI2CCLK
I/O
DVO
DVO I2C Clock:
This signal is used as the I2C_CLK for a digital
display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
tri-stated during a hard reset.
MI2CDATA
I/O
DVO
DVO I2C Data:
This signal is used as the I2C_DATA for a digital
display (i.e. TV-Out Encoder, TMDS transmitter). This signal is
tri-stated during a hard reset.
MDVICLK
I/O
DVO
DVI DDC Clock:
This signal is used as the DDC clock for a digital
display connector (i.e. primary digital monitor). This signal is
tri-stated during a hard reset.
MDVIDATA
I/O
DVO
DVI DDC Data:
The signal is used as the DDC data for a digital
display connector (i.e. primary digital monitor). This signal is
tri-stated during a hard reset.
MDDCDATA
I/O
DVO
DVI DDC Clock:
The signal is used as the DDC data for a digital
display connector (i.e. secondary digital monitor). This signal is
tri-stated during a hard reset.
MDDCCLK
I/O
DVO
DVI DDC Data:
The signal is used as the DDC clock for a digital
display connector (i.e. secondary digital monitor). This signal is
tri-stated during a hard reset.
5.2 Intel 855GM/GME North Bridge(9)
GPIO Signal Descriptions(Continued)
MiTac Secret
Confidential Document
