Microchip Technology PIC16F716, Техническое описание

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2003 Microchip Technology Inc.
Preliminary
DS41206A-page 21
PIC16F716
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (=
1
) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISB bit (=
0
)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 3-2: INITIALIZING PORTB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB0/INT/ECCPAS2 PIN
PORTB pins RB7:RB0 are multiplexed with several
peripheral functions (Table 3-3).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (such as
BSF, BCF, XORWF
) with
TRISB as the destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
1. Perform a read of PORTB to end the mismatch
condition.
2. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
BCF STATUS, RP0 ;select Bank 0
CLRF PORTB ;Initialize PORTB by
;clearing output
;data latches
BSF STATUS, RP0 ;Select Bank 1
MOVLW 0xCF ;Value used to
;initialize data
;direction
MOVWF TRISB ;Set RB<3:0> as inputs
;RB<5:4> as outputs
;RB<7:6> as inputs
Data Latch
RBPU
(1)
P
V
DD
Q D
CK
Q D
CK
Q D
EN
DATA
WR
WR
RD TRIS
RD PORT
weak
pull-up
RD PORT
RB0/INT
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
Note 1: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
V
SS
V
DD
BUS
PORT
TRIS
ECCPAS2: ECCP Auto-shutdown input
RB0/
INT/
ECCPAS2