7I76 20
REFERENCE INFORMATION
SSLBP
COMMAND REGISTER
The commands register is a 16 bit register (right justified in the 32 bit interface) with the
following format:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
M
R
D
S
T
T
T
N
N
N
N
N
N
N
N
W = BIT 15 Write bit, set high for control data write commands
M = BIT 14
ROM enable/ reset bit, set high to reset processor / download ROM
R = BIT 13
Request bit, set high for read or write command
D = BIT 12
DoIt bit, set high for DoIt commands
S = BIT 11 Start/Stop bit, actual operation depends on T:
ST = 1,0,0,0
Stop LBP interface = 0x08NN
ST = 1,0,0,1
Start LBP interface in normal mode = 0x09NN S T =
1,1,1,1
Start LBP interface in setup mode
= 0x0FNN
N bits determine which channels start or do data transfer with remote device. A set
bit indicates that the corresponding channel will start or do a data transfer.
A command is started when written to the command register. Command completion
is signaled by the command register being cleared (to 0x0000) by the internal SSLBP
firmware. If the command register is read before the command is complete, it will reflect
the previously written command. The command register should not be written when non-
zero or unpredictable behavior may result. There are two exceptions to this rule:
1. A STOP ALL command can always be written to reset the SSLBP interface.
2. Command writes with the ignore bit set can always be written (see below)
COMMAND REGISTER WRITE IGNORE
The command register has a feature that any command written with the MSB (bit
31) set will be ignored. This is for compatibility with DMA driven interfaces or any
interfaces that use a fixed address list for low level hardware access so cannot skip writes.
Содержание 7I76
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