Logic-Analyzer Mode
Digital Inputs
16
Simultaneous channels
8 + 8
Measured value memory per channel
100 Samples to 262.000 Sam-
ples
Simultaneous trigger channels
8
Sampling rate
100
kS/s
Delay between the 8-bit groups
2
μ
Time basis
(1
μ
s/S to 10
ms/S in 1
μ
s steps, then
10
ms/S steps)
10
μ
s to 2,5
s
Accuracy (time)
100
ppm
Logic level
5
V CMOS
(1,8
V/3,3
V CMOS; 12
V/24
V;
with optional converter)
Overload protection
+5,5
VDC/-0,5
VDC
Input impedance
50
M
Ω
, 8
pF
Trigger Modes
4
Pattern (low / high / edge rising / edge
falling / ignore) in any combination sim-
ultaneous for 8
bit
✔
Manually
✔
Extern
✔
Delay
✔
Analog Data-Logger-Mode
Analog Input
2
Resolution
16
bit
Nonlinearity, integral
±2
LSB
Sampling rate
2 x 100
kS/s
Simultaneous channels
2
Input voltage range (in 1-2-5-steps)
±100
mV to ±10
V
Analog bandwidth (-3
dB)
500
kHz
Time basis
10
μ
s to 2,5
s