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MeiG_SLM550_Hardware Design Manual
MeiG Smart Technology Co., Ltd
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MIPI_DSI0_LANE3_M
60
I/O
MIPI_DSI0_LANE3_P
61
I/O
MIPI_DSI0_LANE2_M
58
I/O
MIPI_DSI0_LANE2_P
59
I/O
GPIO82_LCD_RESET_N
49
O
LCD reset pin
GPIO81_LCD_TE0
50
I/O
LCD frame sync signal
VREG_L20_2P85
129
O
2.8V power supply
LCD_ID of the module, this pin is internally GPIO. When used as LCD_ID, please confirm the internal
circuit of LCD. If the internal divider of the LCD uses resistor divider, please pay attention to the voltage
to meet the high or low range of GPIO.
MIPI is a high-speed signal line. To avoid EMI interference, it is recommended to place a common-
mode inductor near the LCD side.
Figure 23 LCD interface circuit