MeiG_SLM550_Hardware Design Manual
MeiG Smart Technology Co., Ltd
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GPIO12_DBG_UART_
TX
94
I
UART5 data receive
GPIO13_DBG_UART_
RX
93
O
UART5 data transmit
GPIO69_UART2_TXD 34
I
UART2 data receive
GPIO70_UART2_RXD 35
O
UART2 data transmit
GPIO4_UART2_CTS
36
I
UART2 Clear To Send
(
CTS
)
GPIO5_UART2_RTS
37
O
UART2 Request To Send
(
RTS
)
UIM card Interface
GPIO79_UIM1_DET
22
I
UIM1 insert detect
UIM1_RESET
23
O
UIM1 reset
UIM1_CLK
24
O
UIM1 clock
UIM1_DATA
25
I/O
UIM1 data
GPIO75_UIM2_DET
17
I
UIM2 insert detect
UIM2_RESET
18
O
UIM2 reset
UIM2_CLK
19
O
UIM2 clock
UIM2_DATA
20
I/O
UIM2 data
Front Camera
CSI0_CLK_N
157
I/O
Front Camera MIPI clock
CSI0_CLK_P
196
I/O
CSI0_LN0_N
158
I/O
Front Camera MIPI data
CSI0_LN0_P
197
I/O
CSI0_LN1_N
159
I/O
CSI0_LN1_P
198
I/O
CSI0_LN2_N
160
I/O
CSI0_LN2_P
199
I/O
CSI0_LN3_N
161
I/O