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EOA_INT_SEL = 1, Interrupt on end of acquisition
EOA_INT_SEL = 0, No interrupt on end of acquisition
EOA_INT_SEL is used in conjunction with the residual counter. See BADR3+ 0Dh

EOA = 1, the residual # of samples have been written to the FIFO
EOA = 0, the residual # of samples have not been written to the FIFO
EOA is cleared by writing a 0 to the INT bit. See below.
EOA is in both BADR3+3 and BADR3+4 for convenience in software programming

OVERRUN = 1, FIFO memory has overrun
OVERRUN = 0, FIFO memory has not overrun
OVERRUN is in both BADR3+3 and BADR3+4 for convenience in software programming

INT = 1, Interrupt generated
INT = 0, No interrupt generated
INT must be cleared after each edge sensitive interrupt (EOC, EOB, and EOA) by setting it to 0.

INTE = 1, Interrupts are enabled.
INTE = 0, Interrupts are disabled.
To enable interrupts you must also set bits in BADR1 + 4Ch

A/D PACER CLOCK STATUS AND CONTROL
BADR3 + 5
READ/WRITE

PS0

PS1

EXT_PACER_POL

GATE_EN

GATE_LATCH

GATE_POL

GATE_STATUS

X

0

1

2

3

4

5

6

7

PS[1:0] control the source of the A/D Pacing according to the table below.

Internal Pacer Clock (CTR 2 OUT, no external access)

1

1

External Pacer Clock (Digital input 0, Pin 25)

0

1

Software polled A/D

X

0

PS0

PS1

EXT_PACER_POL = 1, the external pacer polarity is set to negative edge for non burst mode and burst

mode

EXT_PACER_POL = 0, the external pacer polarity is set to positive edge for non-burst mode and burst

mode

This bit is only used when the external pacer clock is selected. We recommend setting to positive edge.

The remainder of the bits are only used when the internal pacer is selected.
Note: The polarity (direction) of the internal pacer is set by a hardware jumper. It is recommended that

it be set to a positive-going edge.

GATE_EN = 1, the gate to the internal pacer is always on regardless of the signal on pin 25. In this

mode, the bits below are ignored.

GATE_EN = 0, the gate to the internal pacer is controlled by the signal on pin 25.

GATE_ LATCH = 1, the signal on pin 25 will act as an edge trigger to the internal pacer. It is latched in

hardware. Software must clear latch by writing a “0” to the GATE_STATUS bit.

GATE_ LATCH = 0, the signal on pin 25 will act as a level gate to the internal pacer.

26

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Содержание PCIM-DAS1602/16

Страница 1: ...PCIM DAS1602 16 ANALOG DIGITAL I O BOARD for the PCI Bus User s Manual Revision 2 Copyright September 2000 ...

Страница 2: ...ossibility of such damages MEGA FIFO the CIO prefix to data acquisition board model numbers the PCM prefix to data acquisi tion board model numbers PCM DAS08 PCM D24C3 PCM DAC02 PCM COM422 PCM COM485 PCM DMM PCM DAS16D 12 PCM DAS16S 12 PCM DAS16D 16 PCM DAS16S 16 PCI DAS6402 16 Universal Library InstaCal Harsh Environment Warranty and Measurement Computing are registered trademarks of Measurement ...

Страница 3: ...nputs 15 5 2 2 Common Ground Differential Inputs 15 5 2 1 Common Ground Single Ended Inputs 14 5 2 WIRING CONFIGURATIONS 12 5 1 2 System Grounds and Isolation 9 5 1 1 Single Ended and Differential Inputs 9 5 1 ANALOG INPUTS 8 5 ANALOG CONNECTIONS 8 4 2 DIGITAL I O CONNECTOR 7 4 1 MAIN CONNECTOR DIAGRAM 7 4 CONNECTOR PIN OUTS 6 3 3 DIRECT REGISTER LEVEL PROGRAMMING 6 3 2 FULLY INTEGRATED SOFTWARE P...

Страница 4: ...This page is blank ...

Страница 5: ...how to configure the various switches and jumpers to match your application requirements and will create a configuration file that your application software and the Universal Library will refer to so the software you use will automatically know the exact configuration of the board Please refer to the Software Installation Manual regarding the installation and operation of InstaCalTM The following ...

Страница 6: ...software when the second board is installed It is best to use a library such as Universal Library or a program such as SoftWIRE DasWizard or Agilent VEE to make measurements with your PCIM DAS1602 16 2 2 1 10 MHz XTAL JUMPER The 1 10 MHz XTAL jumper selects the frequency of the square wave used as a clock by the A D pacer circuitry Figure 2 1 This pacer circuitry controls the sample timing of the ...

Страница 7: ...ck initialization glitching easy to avoid but a real possibility in the DAS 1600 Converting on the falling edge mode also may lead to timing differences if the PCIM DAS1602 16 board is being used as a replacement for an older DAS16 series board Because using the falling edge trigger was undesirable we have designed a jumper into the PCIM DAS1602 16 which allows you choose the edge that starts the ...

Страница 8: ...s of 0 to 5V 0 to 10V 5V 10V Other ranges between 0V and 10V are available if you provide a precision voltage reference at pin 10 D A0 or 26 D A1 of the main connector When the DAC1 reference is supplied onboard pin 26 of the 37 pin connector is unused and can be employed as a SSH simultaneous sample hold trigger for use with the CIO SSH16 To do so place the jumper between the two pins SH Figure 2...

Страница 9: ...tion from the main menu 3 Follow the instructions provided If you do not receive the expected results a make certain you have connected the correct pins according to the connector diagram b go back through the installation procedure and make sure you have installed the board according to the instructions If this does not get you to the desired display please call us or contact your local distribut...

Страница 10: ...Library package 3 2 FULLY INTEGRATED SOFTWARE PACKAGES e g SoftWIRETM Many users now take advantage of the power and simplicity offered by an the upper level data acquisition package such as SoftWIRE or DasWizard SoftWIRE is a new easy to use graphical programming package that runs in Visual Basic Non programmers can build powerful applications without writing any code Experienced programmers can ...

Страница 11: ...t is available at pin 26 It is required when the CIO SSH16 card is used with a PCIM DAS1602 16 Figure 4 1 Figure 4 1 Main Analog Connector Pinout The connector accepts female 37 pin D type connectors such as those on the C73FF 2 a two foot cable with connectors If frequent changes to signal connections or signal conditioning is required we strongly recommend purchasing the CIO MINI37 screw termina...

Страница 12: ...The pinouts of the 40 pin digital I O connector and BP40 37 cable are shown in Figure 4 2 below They are repeated in the Specifications section Figure 4 2 Digital I O Connector Pinout BP40 37 Cable Pinout 8 PORT A 0 PORT A 1 PORT A 2 PORT A 3 PORT A 4 PORT A 5 PORT A 6 PORT A 7 PORT C 0 PORT C 1 PORT C 2 PORT C 3 PORT C 4 PORT C 5 PORT C 6 PORT C 7 GND 5V 37 36 35 34 33 32 31 30 29 28 27 26 25 24 ...

Страница 13: ...o skip to the next section on wiring configurations 5 1 1 Single Ended and Differential Inputs The PCIM DAS1602 16 provides either eight differential or 16 single ended input channels Single Ended Inputs A single ended input measures the voltage between the input signal and ground In this case in single ended mode the PCIM DAS1602 16 measures the voltage between the input channel and LLGND The sin...

Страница 14: ...the input only measures the difference between the two leads and the EMI common to both is ignored This effect is a major reason there is twisted pair wire as the twisting assures that both wires are subject to virtually identical external influence Figure 5 2a and 5 2b below show a typical differential input configuration Figure 5 2a Differential Input Theory 10 Input Amp To A D LL GND CH IN 1 2 ...

Страница 15: ... board This limitation or common mode range is depicted graphically in Figure 5 3 The PCIM DAS1602 16 common mode range is 10 Volts Even in differential mode no input signal can be measured if it is more than 10V from the board s low level ground LLGND Figure 5 3 Common Mode Range 11 Input Amp To A D Differential Input LL GND CH High CH Low Vs Vs Vcm Common Mode Voltage Vcm is ignored by different...

Страница 16: ...s you may have a system with common grounds However since voltmeters will average out high frequency signals there is no guarantee Please refer to the section below titled Common Grounds If you measure reasonably stable AC and DC voltages your system has an offset voltage between the grounds category This offset is referred to as a Common Mode Voltage Please be careful to read the following warnin...

Страница 17: ...er Systems with Common Mode ground offset Voltages The most frequently encountered grounding scenario involves grounds that are somehow connected but have AC and or DC offset voltages between the PCIM DAS1602 16 and signal source grounds This offset voltage may be AC DC or both and can be caused by a wide array of phenomena including EMI pickup resistive voltage drops in ground wiring and connecti...

Страница 18: ...fort during connections to assure optimum performance is obtained Please refer to the following sections for further details 5 2 WIRING CONFIGURATIONS Combining all the grounding and input type possibilities provides us with the following potential connection configurations The combinations along with our recommendations on usage are shown in Table 5 1 below Table 5 1 Input vs Grounding Recommenda...

Страница 19: ...itor a signal source with a common ground is a acceptable configuration though it requires more wiring and offers fewer channels than selecting a single ended configuration Figure 5 5 below shows the recommended connections in this configuration Figure 5 5 Common Ground Differential Inputs 15 Input Am p To A D A D Board I O Connector LL GND CH IN Signal Source with Common Gnd Optional wire since s...

Страница 20: ...IM DAS1602 16 will not directly monitor signals with common mode voltages greater than 10V You will either need to alter the system ground configuration to reduce the overall common mode voltage or add isolated signal conditioning between the source and your board See Figure 5 7 and 5 8 below Figure 5 7 Common Mode Voltage 10V Single Ended Input 16 Input Am p To A D A D Board I O Connector LL GND ...

Страница 21: ...ed to a Differential Input Large common mode voltage between signal source A D board G ND Isolation Barrier W hen the voltage difference between signal source and A D board ground is large enough so the A D board s common mode range is exceeded isolated signal conditioning must be added Input Am p To A D A D Board I O Connector LL GND CH High CH Low 10 K 10K is a recom m ended value You may short ...

Страница 22: ... proportional to the digital value in the output register For example in unipolar mode the supplied reference of 5V provides a 5V output actually 4 9988V when the value in the output register is 4095 full scale at 12 bits of resolution It provides a value of 2 5V when the value in the output register is 2048 Figure 5 11 shows the onboard reference internally jumpered Both D A outputs will have a r...

Страница 23: ...Figure 5 11 Analog Output Range Select Jumper Block 19 Bipolar Unipolar Select Jumpers D A0 D A1 RangeJumper Block ...

Страница 24: ... different machines Assigned by the PCI BIOS these Base Address values cannot be guaranteed to be the same even on subsequent power on cycles of the same machine All software must interrogate BADR0 at run time with a READ_CONFIGURATION_DWORD instruction to determine the BADRn values BADR0 and BADR1 are used for PCI configuration Only the PCI Interrupt Control Status Register BADR1 4Ch should be us...

Страница 25: ...itive interrupts EndOfAcquisition EndOfBurst and EndOfConversion must be cleared by writing a 0 to the INT bit in BADR3 4 This must be done at the end of your interrupt service routine The level sensitive interrupts FifoHalfFull and FifoNotEmpty will be regenerated after you service the interrupt if their condition is still true See the section on BADR3 4 for more details 6 3 BADR2 REGISTERS DAC 1...

Страница 26: ...AC 1 Data WRITE ONLY DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSB LSB DA 11 0 These bits represent the DAC data word Format is dependent upon offset mode as described below 10V Range Vref 10V 5V Range Vref 5V Bipolar Mode Offset Binary Coding 000 h Vref 7FFh Mid scale 0V FFFh Vref 1 LSB Vref 0V Vref 1 LSB Vref 0V Unipolar Mode Straight Binary ...

Страница 27: ...ettings BADR3 2 Main Connector Digital Outputs Main Connector Digital Inputs BADR3 1 Mux scan limits Mux scan limits BADR3 0 WRITE FUNCTION READ FUNCTION REGISTER MUX SCAN LIMITS REGISTER BADR3 0 READ WRITE CH L0 CH L1 CH L2 CH L3 CH H0 CH H1 CH H2 CH H3 0 1 2 3 4 5 6 7 READ The current channel scan limits are read as one byte The high channel number scan limit is in the most significant four bits...

Страница 28: ...ove NOTE The digital lines 0 3 pins 3 4 5 6 22 23 24 25 of the analog connector should not be used as ON OFF Digital I O See below The digital inputs have multiple functions as described above The digital outputs are also used by the CIO EXP32 32 channel analog multiplexor amplifier There is a 24 line 82C55 on general purpose digital I O see BADR4 We suggest that the Main connector 4 bit ports be ...

Страница 29: ...O EOA is cleared by writing a 0 to the INT bit in BADR3 4 See below EOA is in both BADR3 3 and BADR3 4 for convenience in software programming FNE 1 FIFO memory contains at least on sample FNE 0 FIFO memory contains no samples FHF 1 FIFO memory contains at least 512 samples FHF 0 FIFO memory contains less than 512 samples OVERRUN 1 FIFO memory has overrun OVERRUN 0 FIFO memory has not overrun OVER...

Страница 30: ...ntrol the source of the A D Pacing according to the table below Internal Pacer Clock CTR 2 OUT no external access 1 1 External Pacer Clock Digital input 0 Pin 25 0 1 Software polled A D X 0 PS0 PS1 EXT_PACER_POL 1 the external pacer polarity is set to negative edge for non burst mode and burst mode EXT_PACER_POL 0 the external pacer polarity is set to positive edge for non burst mode and burst mod...

Страница 31: ...its in BADR3 0 are used to specify the channels in the burst BME 0 Bursting is disabled The burst mode generator is a clock signal that paces the A D at the maximum multi channel sample rate then periodically performs additional maximum rate scans In this way the channel to channel skew time between successive samples in a scan is minimized without taking a large number of undesired samples Figure...

Страница 32: ... 5 6 7 The 82C54 counter 1 is available to you as a generic counter timer The clock gate and output are all available at the main 37 pin connector Refer to BADR3 0C HEX for clock options 8254 COUNTER 2 DATA ADC PACER LOWER COUNTER BADR3 9 READ WRITE D1 D2 D3 D4 D5 D6 D7 D8 0 1 2 3 4 5 6 7 82C54 COUNTER 3 DATA ADC PACER UPPER COUNTER BADR3 0Ah READ WRITE D1 D2 D3 D4 D5 D6 D7 D8 0 1 2 3 4 5 6 7 Coun...

Страница 33: ...multiple of half the FIFO size 512 or the total number of samples is less than the FIFO size 1024 Always write the residual count before setting the EOA_INT_SEL bit Writing to either register will reset the counter with the new values You must write the values each acquisition even if they have not changed Use the following rules for correct operation Total number of samples is less than 512 1 Bef...

Страница 34: ... 03h to BADR3 4 Total number of samples is greater than 1024 1 Before you start the acquisition write the residual number of samples to the residual counter an 83h to BADR3 4 INTE and FIFO_HALF FULL enabled and a 67h to BADR1 4Ch INTE and PCINTE enabled The residual number of samples is the remainder of the total number of samples divided by 512 2 Start the acquisition 3 The first interrupt you ge...

Страница 35: ...e a 03h to BADR3 4 read 1 sample from FIFO and then write another 03h to BADR3 4 6 5 BADR4 PORT I O REGISTERS Table 6 2 BADR4 Port I O Registers 82C55 Control Register None BADR4 3 82C55 Port C Output 82C55 Port C Input BADR4 2 82C55 Port B Output 82C55 Port B Input BADR4 1 82C55 Port A Output 82C55 Port A Input BADR4 0 WRITE FUNCTION READ FUNCTION REGISTER There are 24 Digital I O ports from an 8...

Страница 36: ... 4 20 32 5 40 64 6 80 128 7 HEX DECIMAL BIT Port C can be used as one 8 bit port of either input or output or it can be split into two 4 bit ports which can be independently input or output The notation for the upper 4 bit port is PCH3 to PCH0 and for the lower PCL3 to PCL0 Although it can be split every read and write to port C carries eight bits of data so unwanted information must be ANDed out ...

Страница 37: ... 0 is mode 0 for group B Input Output M1 1 is mode 1 for group B Strobed Input Output All four groups can be independently programmed in one of several modes The most commonly used mode is mode 0 input output mode The codes for programming the 82C55 in mode 0 are shown in Table 6 4 Table 6 4 Mode 0 Configuration Codes for 82C55 IN IN IN IN 155 9B 1 1 1 1 OUT IN IN IN 154 9A 0 1 1 1 IN OUT IN IN 15...

Страница 38: ...d to have the cover off your computer with the power on so trim pots can be adjusted during calibration using a jeweler s screwdriver 7 2 CALIBRATING THE A D D A CONVERTERS The A D is calibrated by applying a known voltage to an analog input channel and adjusting trim pots for offset and gain There are three trim pots requiring adjustment to calibrate the analog input section of the card There are...

Страница 39: ...is to choose two resistors with the proper proportions relative to the full scale of the analog or digital input and the maximum signal voltage Figure 8 1 Figure 8 1 Voltage Divider Schematic Reducing a voltage proportionally is called attenuation The formula for attenuation is R1 R2 The variable Attenuation is the Attenuation proportional difference between the R2 signal voltage max and the full ...

Страница 40: ...sitions which you can complete with the proper value components for your application 8 2 LOW PASS FILTERS A low pass filter is placed on the signal wires between a signal and an A D board It stops frequencies greater than the cut off frequency from entering the A D board s analog or digital inputs The key term in a low pass filter circuit is cutoff frequency The cutoff frequency is that frequency ...

Страница 41: ...INSW Data Transfer Software selectable option burst interval 10uS Burst Mode TTL output pin 26 jumper enabled Logic 0 Hold Logic 1 Sample Compatible with CIO SSH16 Simultaneous Sample and Hold Trigger External gate pin 25 High or Low level software selectable A D Gate only available when internal pacing selected software enable disable External edge trigger pin 25 Positive or negative edge softwar...

Страница 42: ...ax 2 0 LSB C max 2 2 LSB C max 2 500V 4 1 LSB C max 1 9 LSB C max 2 2 LSB C max 5 000V 4 0 LSB C max 1 8 LSB C max 2 2 LSB C max 10 00V Overall Analog Input Drift Analog Input Zero Drift Analog Input Full Scale Gain Range Absolute error change per C Temperature change is a combination of the Gain and Offset drift of many components The theoretical worst case error of the board may be calculated by...

Страница 43: ...ode 0 code 0V 4095 code Vref 1LSB Vref 0V Vref 1LSB Vref 0V Coding Any passive load Output Stability 0 1 ohms max Output impedance DC Output coupling Indefinite 25mA Output short circuit duration 5 mA min Current Drive 30uS max to LSB for a 20V step Settling Time 2 0V µs min Slew Rate Guaranteed monotonic over temperature Monotonicity System dependent Using the Universal Library programmed output ...

Страница 44: ...etical worst case error of the board may be calculated by summing these component errors Worst case error is realized only in the unlikely event that each of the component errors are at their maximum level and causing error in the same direction Digital Input Output Section Digital I O Connector 24 Number of I O 82C55 Digital Type 2 banks of 8 with handshake 3 banks of 8 or 2 banks of 8 and 2 bank...

Страница 45: ...n connector pin 25 Counter 3 Gate software enable disable Counter 2 Output Counter 3 Source Internal only chained to Counter 3 Source Counter 2 Output External source from main connector pin 25 Counter 2 Gate software enable disable Internal 10 MHz Internal 1 MHz Counter 2 Source jumper selectable Available at main connector pin 2 Counter 1 Output External gate from main connector pin 24 Counter 1...

Страница 46: ...IG IN 3 5 DIG OUT 0 23 DIG OUT 1 4 DIG OUT 2 22 DIG OUT 3 3 CTR 1 CLOCK IN 21 CTR 1 OUT 2 CTR 3 OUT 20 5V PC BUS POWER 1 Signal Name Pin Signal Name Pin Single Ended Analog Input Mode AGND 19 CHO HIGH 37 CH8 HIGH 18 CH1 HIGH 36 CH9 HIGH 17 CH2 HIGH 35 CH10 HIGH 16 CH3 HIGH 34 CH11 HIGH 15 CH4 HIGH 33 CH12 HIGH 14 CH5 HIGH 32 CH13 HIGH 13 CH6 HIGH 31 CH14 HIGH 12 CH7 HIGH 30 CH15 HIGH 11 AGND 29 D ...

Страница 47: ...A 1 34 DIG GND 33 PORT A 2 32 NC 31 PORT A 3 30 DIG GND 29 PORT A 4 28 NC 27 PORT A 5 26 DIG GND 25 PORT A 6 24 NC 23 PORT A 7 22 DIG GND 21 PORT C 0 20 PORT B 0 19 PORT C 1 18 PORT B 1 17 PORT C 2 16 PORT B 2 15 PORT C 3 14 PORT B 3 13 PORT C 4 12 PORT B 4 11 PORT C 5 10 PORT B 5 9 PORT C 6 8 PORT B 6 7 PORT C 7 6 PORT B 7 5 DIG GND 4 NC 3 5V PC BUS POWER 2 NC 1 Signal Name Pin Signal Name Pin 43...

Страница 48: ...For your notes 44 ...

Страница 49: ...ative documents EU EMC Directive 89 336 EEC Essential requirements relating to electromagnetic compatibility EU 55022 Class B Limits and methods of measurements of radio interference characteristics of information technology equipment EN 50082 1 EC generic immunity requirements IEC 801 2 Electrostatic discharge requirements for industrial process measurement and control equipment IEC 801 3 Radiate...

Страница 50: ...Measurement Computing Corporation 16 Commerce Boulevard Middleboro MA 02346 Telephone 508 946 5100 Fax 508 946 9500 E mail info MeasurementComputing com www MeasurementComputing com ...

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