Measurement Computing PCIM-DAS1602/16, Руководство пользователя

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6.4 BADR3 REGISTERS
Residual Counter lower byte
BADR3 + 0Eh
Residual Counter upper 2 bits BADR3 + 0Dh
User Counter Clock Control User Counter Clock Setting
BADR3 + 0Ch
82C54 Counter Control Data 82C54 Counter Control Data BADR3 + 0Bh
82C54 Counter 3 Data 82C54 Counter 3 Data BADR3 + 0Ah
82C54 Counter 2 Data 82C54 Counter 2 Data
BADR3 + 9
82C54 Counter 1 Data 82C54 Counter 1 Data BADR3 + 8
Programmable Gain Control Programmable Gain Settings BADR3 + 7
Burst Mode and Converter Control Burst Mode and Converter Settings BADR3 + 6
A/D Pacer Clock Control A/D Pacer Clock Settings BADR3 + 5
Interrupt Control Interrupt Settings /Status
BADR3 + 4
ADC Conversion Status BADR3 + 3
ADC Channel Status and Switch Settings BADR3 + 2
Main Connector Digital Outputs Main Connector Digital Inputs
BADR3 + 1
Mux scan limits Mux scan limits BADR3 + 0
WRITE FUNCTION READ FUNCTION REGISTER
MUX SCAN LIMITS REGISTER
BADR3 + 0
READ/WRITE
CH L0 CH L1 CH L2 CH L3 CH H0 CH H1 CH H2 CH H3
0 1 2 3 4 5 6 7
READ
The current channel scan limits are read as one byte. The high channel number scan limit is in the most
significant four bits. The low channel scan limit is in the least significant four bits.
WRITE
The channel scan limits desired are written as one byte. The high channel number scan limit is in the
most significant four bits. The low channel scan limit is in the least significant four bits.
Every write to this register sets the current A/D channel MUX setting to the number in
bits 0-3 and resets the FIFO. You should delay 10
µ
s after setting the MUX (to allow for
settling time) before initiating a conversion.
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