MATSONIC MS9118E Series, Руководство пользователя

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Mainboard User’s Manual
buffered, to compensate for the speed
differences between the CPU and PCI bus;
PCI Master 0 WS Write : When enabled,
writes to the PCI bus are executed with zero
wait states;
PCI Delay Transaction : The
chipset’s embedded 32-bit post write buffer
support delay transactions cycles. Select
Enabled to support compliance with PCI
specification version 2.1.
Memory Hole You can reserve this area of system memory
for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user
information of peripherals that need to use
this area of system memory usually
discusses their memory requirements.
System BIOS
Cacheable When enabled, the System BIOS will be
cached for faster execution.
Video RAM
Cacheable When enabled, the graphics card’s local
memory will be cached for faster execution.
However, if any program writes to this
memory area, a system error may result.
Delay Prior To
Thermal Enables you to set the delay time before the
CPU enters auto thermal mode.
VGA Share
Memory Size This item enables you to specify the system
memory size to allocate to the video memory.
FB Address
Conversion This feature optimizes the memory address
table for VGA frame buffer accesses
according to the DRAM page size in use.
Enabling this item improves VGA
performance especially in tiling address
mode. This feature cannot be used
simultaneously with CPU direct FB access
mode.
FB Page Close
Prediction When enabled, this feature automatically
closes frame-buffer DRAM pages no longer
needed in tiling address mode. Enabling this
item improves DRAM related performance in
tiling address mode. This feature has
maximum effect when the previous field (FB
Address Conversion) is enabled at the same
time.
Press <Esc> to return to the previous screen.
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