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Processing FPGA 55
Processing FPGA
To reduce the number of image processing tasks that the Host CPU must perform,
Matrox Radient eCL has a Processing FPGA. The Processing FPGA can be
configured to offload and even accelerate the most compute-intensive part of
typical image processing applications, without generating additional data traffic
within the host computer (Host).
Before the Processing FPGA can process grabbed images, they must be stored in
main on-board memory. If images stored in Host memory are required, they can
be streamed directly to the Processing FPGA for processing. Images resulting from
Processing FPGA processing can be stored in main on-board memory or streamed
to the Host.
The maximum bandwidth for image streamed directly to/from Host memory is
1 Gbytes/sec, while it is 2 Gbytes/sec for images streamed to/from on-board
memory.
Possible processing operations
To use the Processing FPGA, you must configure it with an FPGA configuration
that defines the appropriate functionality. An FPGA configuration is a code
segment that is used to program an FPGA. You would typically use standard
Matrox FPGA configurations. If required, Matrox’s FPGA design services can be
employed to generate an application-specific FPGA configuration.
Once the Processing FPGA is programmed, you can then make use of its
functionality using MIL. Refer to
Using MIL with a Processing FPGA chapter in
the MIL User Guide for more information.