Matrox Radient eCL-DF, Установка и справочник по оборудованию, Страница: 39 / 96

Matrox Radient eCL acquisition section 39
Demultiplexers to support time-multiplexed video sources
Each acquisition path of the board features a demultiplexer. It can deserialize input
from time-multiplexed video sources on a clock cycle basis. Time-multiplexed
video sources can output larger pixel depths and more taps than are possible with
non-time-multiplexed video sources in the same configuration (with the same
amount of cabling). When enabled, the demultiplexer assumes that two video
streams share the same data path and that the streams are interleaved based on the
clock cycle. The demultiplexer assumes that on one clock cycle, the data is from
one stream and that on the next clock cycle, the data is from another stream. The
demultiplexer can only deserialize video inputs that, when combined and, if
necessary, expanded, total a maximum depth of 64 bits per acquisition path.
Expansion refers to the automatic addition of padding zeros on the most
significant bits (MSB) of 10-, 12-, and 14-bit data to create byte aligned 16-bit
data. Expansion is not always necessary.
For each acquisition path, two LVDS pairs are used to transmit and receive
asynchronous serial communication between the video source and the board.
These signals are handled by the Universal Asynchronous Receiver/Transmitters
(UARTs).
For each acquisition path, four camera control output signals are also available.
These are general-purpose signals that are sent to the video source.
UARTs
For each acquisition path, Matrox Radient eCL offers an LVDS-compatible
Matrox serial interface. Each interface is mapped as a COM port so that it can be
accessed through the Win32 API. Each interface is comprised of both a transmit
port and a receive port, permitting the interface to work in full-duplex
(bidirectional) mode. The interfaces are located on the Camera Link connectors.
Each interface is controlled by a Universal Asynchronous Receiver-Transmitter
(UART)
*
. Each UART features independently programmable baud rates,
supporting all standard baud rates from 300 baud up to 115200
†
baud.
*. The UART implementation was derived from a design by Daniel Wallner. Please see
Appendix C: Acknowledgments for copyright information.
†. In addition, the maximum baud rate is highly dependent on the amount of computer
resources available.