MODEL 2350-1 Data Logger
17
3. THEORY OF OPERATION
3.1.5 DIGITAL TO ANALOG CONVERTORS
U6 and U7 are digital to analog convertors
(DAC) which convert the digital data from the µP to
analog signals to control the THR, WIN, High
Voltage Reference (HV REF), and Overload
Reference (OVR REF) variables. Data via BUS0-
BUS3 and A0-A2 is loaded into the DAC latches
for U6 and U7 by strobing CE3' and CE4' (Chip
Select). CE5' (Up Date) is then strobed to transfer
the data stored in the latches to the DAC outputs.
3.1.6 HIGH VOLTAGE SUPPLY AND
DETECTOR OVERLOAD
Detector High Voltage (HV) is developed
by blocking oscillator Q3, T1, C29 and rectified by
voltage multiplier CR3-CR5, CR14, CR15, C5,
C32, C37, and C38. Q4, CR13, and R41 provide
a regulated voltage of approx. 4.4 Vdc (battery
voltage must be +4.4 Vdc) to the emitter of Q3.
HV increases as current through Q5 increases
with maximum output voltage with Q5 saturated.
HV is coupled back through R5, through
voltage follower U1, to pin 6 of U2 to complete the
regulation loop. Resistors R52 and R6 complete
the HV divider network to ground. HV regulation is
produced by opamp comparator pins 5, 6, and 7 of
U2. During stable operation the voltage at pin 6 will
equal pin 5. If HV REF is increased, pin 7 of U2
will increase increasing conduction of Q5 until the
voltage at pin 6 equals pin 5 of U2 via HV divider
network, R5, R52, and R6. R52 is adjusted to
calibrate the HV output to the HV REF signal
supplied to pin 5 of U5 by the DAC — HV REF is
set at approx. 1500 mV by entering the “H1500"
command into the Model 2350-1, the HV CAL is
adjusted for 1500 Vdc at the detector connector.
C1-C3, C8-C7, C19, and C27 provide additional
filtering of the HV output.
Detector Overload is achieved by
measuring the voltage differential across R4. As
current is increased into the detector, a voltage
drop is produced across R4. The HV on either side
of R4 is converted to a low voltage by resistor
divider networks R5, R52, R6, and R44, R7, and
R43. The voltage differential is coupled to
differential opamp, pins 12-14 of U1, via opamp
buffers. The differential output is coupled to
opamp comparator, pins 8- 10 of U1. OVR REF is
provided by the µP via the DAC — OVERLOAD’ is
coupled back to the µP. R7, CURRENT CAL,
calibrates the detector current drain to the OVR
REF input — i.e., a 10µA load is connected to the
detector output; the overload is set to “100" by
entering the “O100" command (approx. 610mV at
OVR REF), R7, CURRENT CAL, is then adjusted
until pin 8 or U1 just starts to trigger low.
3.1.7 LOW VOLTAGE SUPPLY
Supply voltages of +5 and -10 Vdc are
supplied by U8, T2, and supporting components.
U8 is a switching regulator with an on-board
comparator providing regulation. An internal
voltage reference of 1.0 Vdc maintains the
inverting and non-inverting comparators at 1.0V
via the feedback loop. Oscillator frequency, set by
C36, is approx. 100 kHz at pin 5 of U5. CR11 and
C26 provide rectification and filtering for the +5V
output. CR12 and C25 provide rectification and
filtering for the -10V output.
U11 is a -2.5 Vdc voltage reference for the
DAC’s — U6 and U7. C8 located on the Backplane
board maintains the battery voltage charge during
inadvertent battery disconnection (mechanical
shock).
3.1.8 LCD VIEWING ANGLE SUPPLY
U2 is configured as a differential opamp
which controls the backplane voltage to adjust the
viewing angle for the LCD graphics display.
Output voltage, pin 1 of U2 is adjustable from 0 to
-10 Vdc by varying R50 (VIEWING ANGLE). LCD
backplane variance due to temperature is
compensated by CR10.
Содержание 2350-1
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