MODEL 2350-1 Data Logger
18
3. THEORY OF OPERATION
3.2 CENTRAL PROCESSOR BOARD #5371-068
I/O board to reset the I/O processor. Q174 inverts
the RESET signal (RESET’) providing a reset line
for the LCD graphics display. The PULSE’ input
supplies the pulses from the AMP/PS board to be
counted and converted into data by the µP.
3.2.2 BATTERY VOLTAGE VFC
Un-switched (connected directly to
batteries) battery voltage — +BATUNS — is
divided by resistor divider network R148 and R149
and connected to voltage to frequency convertor
(VFC), U125. VFC OUT is connected to a counter
inside the µP which counts the frequency for a
preset time converting to a number displayed on
the LCD representing the battery voltage. R130,
BAT CAL, adjusts the VFC frequency output to
calibrate the LCD BAT reading to the actual
battery voltage.
NOTE: Disregard sections 3.2.3 and 3.2.4 for the
Model 2350-1
3.2.3 RECORDER DRIVE CIRCUIT
The RCDR output from the µP is coupled
to MOSFET transistor Q126. The µP uses pulse-
width modulation for the recorder signal. The
pulse-modulated signal is integrated by R144 and
C100. Pins 5, 6, and 7 of U126 “buffers” the
integrated voltage from R131. R131 provides
calibration of the recorder output voltage. Pins 1,
2, and 3 of U126 are configured as an opamp
voltage follower providing recorder drive.
3.2.4 ADDRESS DECODER/VOLTAGE
BACKUP
U120 is address decoder which generates
the chip enable signals — CEO-CE7 — by
monitoring address lines A13-A15. U120 also
provides battery backup, +5VBACK, to the Clock
chip U119 and the RAM U123. This enables the
user to change the instrument batteries without
losing RAM memory. +BATUNSR supplies
battery voltage to CR112 voltage reference to limit
the voltage at 5.1 Vdc. The 5.1 Vdc is coupled to a
0.1
3.2.1 MICROPROCESSOR (µP)
U124, Intel 80C51FA, is the Model 2350-1
central processor. The µP clock frequency is
crystal controlled by Y159 and related components
at 6.144 MHZ. C172 resets the µP at power-up to
initiate the start of the program routine. The main
program routine is stored in EPROM, U122. User
parameters and logged data is stored in the 8k X
8 RAM, U123. (replaced with 64k X 8 RAM located
on the Memory Expander board)
Address and data information are
multiplexed by latch U121 from the µP to the two
memory chips. The low address bits A0-A7 are
multiplexed with the data bus, BUS0-BUS7, out of
the µP. U121 latches the address data AO-A7 on
lines BUS0-BUS7 during the first part of the
external memory cycle when the ALE input is
strobed.
The HD175 ACCESS shunt configures the
µP parameter access mode and password. When
pins 1 and 2 are shunted (default) the access
parameters is determined by the settings preset in
the EPROM and the password entered in RAM. If
shunt is placed between pins 2 and 3 the
password is set to “0" and the access level is set
to “3".
The ACKNOWLEDGE’ input is pulled low
when the front panel ACKNLDGE pushbutton
switch is depressed silencing the audible
alarm(s). The OVERLOAD’ signal from the AMP/
PS board instructs the µP to initiate an
OVERLOAD condition. WIN OFF’ is an output
signal from the µP to the AMP/PS board which
disables the Window feature.
The TONE’ input comes from the I/O
processor which toggles the TONE’/ALARM line
low when the external bar code wand registers bar
code information. The TONE’ and ALARM’ (µP
output signal from pin 5 of U124) signals initiate an
independent audible tone by changing the CV
(control voltage) input on the ICM7556 timer,
U118.
The READY, CLEAR SEND, RECEIVE,
and XMIT data lines communicate the RS-232
and bar code reader wand information from/to the
I/O processor to/from the central processor. The
RESET output at pin 13 of U124 is coupled to the
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