MODEL 2350-1 Data Logger
16
3. THEORY OF OPERATION
3.1 AMPLIFIER/POWER SUPPLY BOARD #5371-002
voltage at pin 5, pin 7 — normally high (approx. +5
Vdc) goes low for the pulse duration.
Window (WIN) comparator, pins 1, 2, and
3 of U4 provide the upper pulse height
discrimination. Pulses are coupled from amplifier
U3 to pin 2 of U4. WIN reference voltage data from
the µP is processed by DAC U6 and coupled to pin
3 of U4. Q2 applies approx. +5 Vdc to the WIN
reference to disable the WIN comparator when
the WIN OFF signal is applied to the base of Q2.
The WIN reference voltage rides on top of the
THR reference — i.e., with a THR and WIN setting
of 100, the WIN reference at pin 3 of U4 will equal
approx. +122 mV referenced above the THR at
pin 5 or approx. +244 mV referenced to chassis
ground. If the THR is increased to 200 and the
WIN still remains at 100 the WIN reference will still
equal approx. +122 mV referenced to the
threshold but will increase to approx. +366 mV
when referenced to ground (THR = 244 mV + 122
mV WIN = 366 mV). As the pulse amplitude
increases above the WIN reference voltage, pin 1
of U4 goes low for the pulse duration.
3.1.4 WINDOW/THRESHOLD LOGIC
CIRCUIT
Negative pulses from the THR comparator
are coupled to univibrator U9. Negative, pulses
(approx. 5 volt) are present at univibrator output
pin 7 of U9 (PULSE’) as long as pins 13 and 3
remain high. When a WIN pulse is present at pins
13 and 3 the Reset function is enabled which
disables the PULSE’ output locking pin 7 high.
Pulses are connected from pin 7 to the µP on the
Central Processor Board for count processing.
Pin 7 is tied back to pin 13 via CR1 to provide a
time delay (approx. 8 to 10 µs) for the µP clock
cycle to complete before the next pulse can be
recognized by the micro-processor.
3.1.1 INPUT
Negative going pulses are coupled from
the detector through C9 to emitter follower Q1.
CR6 is a voltage reference which provides a bias
voltage of approxi3.3 Vdc to Q1 via R45.
R9 protects Q1 from input inadvertent shorts/
transients. R40 couples the detector to the high
voltage supply (HV).
3.1.2 AMPLIFIER
U3 is a self-biased amplifier which
provides gain in proportion to R12 divided by the
series combination of R11 and R10. R10 is
adjusted to provide a pulse height in proportion to
a given threshold setting at comparator U4
(typically adjusted to trigger with a detector input
pulse of 10 millivolts at a threshold setting of 100).
Transistor (pins 4, 5, and 6 of U3) provide
amplification and pulse polarity inversion.
Transistor pins 10 through 15 are coupled as a
constant current source to pin 6 of U3. The output
self-biases to 2 Vbe — approximately 1.4 Vdc at
pin 7 of U3. This provides just enough bias current
through pin 6 to conduct all of the current from the
constant current source. Positive pulses from pin
7 are coupled to the Window and Threshold
comparators, U4.
3.1.3 WINDOW/THRESHOLD
Threshold (THR) comparator, pins 5, 6,
and 7 of U4, provides the lower pulse height
discrimination. Pulses are AC coupled from
amplifier U3 via C23 to pin 6 of U4. THR reference
voltage data from the microprocessor board (µP)
is processed by digital to analog convertor (DAC)
U6 and coupled to pin 5 of U4 via opamp U5. R54
and C13 provide additional filtering of the
reference voltage. THR reference Vdc is approx.
+122 millivolts (mV) with the THR set at 100 on
display — 1.222 Vdc at a THR setting of 1000. As
the pulse height at pin 6 of U4 increases above the
reference
Содержание 2350-1
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