Lucent Technologies DSP1611, Информационное руководство

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 External Memory Interface
Lucent Technologies Inc.
DRAFT COPY
6-17
6.4 Timing Examples
Table 6-15 lists the different cases shown in the functional timing diagrams. These diagrams are intended to show
function and not timing requirements to nanosecond accuracy. For timing requirements, see the appropriate DSP
data sheet. Cause and effect arrows are shown for the interactions between the DSP and the external memory.
Timing edges not labeled with cause and effect arrows can be assumed to be driven by the DSP and are coincident
with CKO.
6.4.1 CKO Timing
Figure 6-3 shows two of the six options available for the output clock (CKO). Either option appears on the output
pin depending on the programming of 3 bits in the ioc register (see Section 6.2, Programmable Features ). The
free-running CKO is the frequency of CKI divided by two (2x input clock option). It will have a 50% duty cycle within
the accuracy of the rise and fall times. If wait-states occur, the wait-stated CKO period is (w + 1) times the period
of the free-running CKO. Wait-states occur during external memory cycles and when there is a simultaneous
access to X space and Y space in the same bank of RAM. The duty cycle will also be 50%. The CKO continues to
follow the options in
Table 6-14 during the sleep state induced by setting the AWAIT bit in the alf register.
5-4162
Figure 6-3. CKO Timing
Table 6-15. Index of Timing Examples
Figure Condition Shown
6-3 CKO Timing, Free-Running and Wait-Stated
6-4 Write, Read, Read, (w = 0)
6-5 Read, Write, Write, (w = 0)
6-6 Read (w = 0), Write (w = 0) Compound Address
6-7 Read (w = 1), Read (w = 2)
6-8 Write (w = 1)
6-9 Read Followed Immediately by a Read, Delayed Enable
6-10 Write Followed Immediately by a Read, Delayed Enable, and no Write Hold Time
EXTERNAL MEMORY CYCLE
W = 1
CKI
CKO
(FREE-RUNNING)
CKO
(WAIT-STATED)