Lucent Technologies DSP1611, Информационное руководство

Страница: 198 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 External Memory Interface
Lucent Technologies Inc.
DRAFT COPY
6-21
6.4 Timing Examples
(continued)
6.4.5 Read W = 1, Read W = 2
Figure 6-7 illustrates a read cycle of EROM with a wait-state of one followed one cycle later by an ERAMLO read
cycle with a wait-state of two. All timing events are coincident with the falling edge of CKO. At the beginning,
EROM goes low enabling the external instruction/coefficient memory. The address is placed on the address bus by
the DSP, and the external memory can now come out of 3-state and later place data on the data bus. At the end of
the first read cycle, EROM goes high and the external memory will respond by 3-stating the data bus. The EROM
address remains valid until the next valid address is required. Sometime later, one CKO period in this example, the
next read cycle starts. ERAMLO goes low selecting the external data memory that responds by starting its cycle.
The ERAMLO address is placed on the address bus by the DSP. Later in the cycle, the external memory writes
valid data to the data bus. The cycle ends three CKO periods (w = 2) later with ERAMLO going high, and the exter-
nal memory responds by 3-stating the data bus.
5-4166
Figure 6-7. Read, Read
Sample Instructions:
mwait=0x1002 /*EROM W=1, ERAMLO W=2 */
y=a1 x=*pt++ /*One-cycle read with W=1, pt points to EROM*/
a0=y /*One-cycle instruction, no action on EMI */
y=*r0++ /*One-cycle read with W=2, r0 points to ERAMLO*/
CKO
EROM
DB
RWN
READ CYCLE W = 1
AB
EROM ADDRESS ERAMLO ADDRESS
EROM DATA ERAMLO DATA
ERAMLO
READ CYCLE W = 2