Lucent Technologies DSP1611, Информационное руководство

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
External Memory Interface April 1998
6-24
DRAFT COPY
Lucent Technologies Inc.
6.4 Timing Examples
(continued)
6.4.8 Write, Read, with Delayed Enable
Figure 6-10 illustrates a write followed immediately by a read of the same external memory. This example demon-
strates the use of the delayed enable to prevent bus contention. The leading edge of ERAMLO is delayed one-half
of a CKO period in both cycles to provide 3-state periods for the DSP and the external memory to exchange control
of the data bus. The delay is selected by programming a bit in the ioc register (see
Section 6.2, Programmable
Features ). Another point of this example is to show that the DSP does not provide extra hold time in the write
cycle. Normally, there is an extra CKO period of hold time after the end of the write cycle; but if the DSP knows that
a read cycle follows immediately, it must 3-state the data bus to allow time for the external memory to start driving
the bus.
5-4169
Figure 6-10. Write, Read, with Delayed Enable, No Hold Time
Sample Instructions:
mwait=0x0001 /* ERAMLO W=2 */
*r0++=a0 /* Two-cycle write, r0 points to ERAMLO */
y=*r1++ /* One-cycle read, r1 points to ERAMLO */
CKO
ERAMLO
DB WRITE DATA
RWN
WRITE CYCLE W = 1
AB
READ DATA
READ CYCLE W = 1
WRITE ADDRESS READ ADDRESS