Lucent Technologies DSP1611, Информационное руководство

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 External Memory Interface
Lucent Technologies Inc.
DRAFT COPY
6-19
6.4 Timing Examples
(continued)
6.4.3 Read, Write, Write, W = 0
Figure 6-5 illustrates read, write, write with zero wait-states. This example shows that the instructions causing
memory writes are two-cycle instructions (except if compound addressing is used). From the viewpoint of the EMI,
one-cycle dead zones appear before each write cycle. The ERAMHI enable goes low for each cycle and goes high
between cycles. The address bus is valid during each cycle and remains valid until the next cycle starts. The data
bus (DB) is driven by data from the external memory during the read cycle. During the first half of the write cycle,
the DSP 3-states the DB and writes the DB during the second half of the write cycle. Valid data is held on DB for
one more CKO period to ensure hold time for the external memory. RWN is low during the write cycles.
5-4164
Figure 6-5. Read, Write, Write, W = 0
Sample Instructions for the Above Sequence:
y=*r0++ /* One-cycle read, r0 points to ERAMHI */
*r1++=a0 /* Two-cycle write, r1 points to ERAMHI */
*r1++=a0l /* Two-cycle write, r1 points to ERAMHI */
CKO
AB
DB
READ
DATA
RWN
READ CYCLE
W = 0
WRITE CYCLE
W = 0
WRITE CYCLE
W = 0
WRITE ADDRESS WRITE ADDRESS
WRITE DATA WRITE DATA
ERAMHI
READ ADDRESS
DEAD
ZONE
DEAD
ZONE