Lucent Technologies DSP1611, Информационное руководство, Страница: 191 / 443

DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
External Memory Interface April 1998
6-14
DRAFT COPY
Lucent Technologies Inc.
6.2 Programmable Features
(continued)
Selection of CKO: Bits 13, 8, and 7 in the ioc register are CKO2, CKO1, and CKO0.
Table 6-14 shows the options
for CKO.
Note: The phase of CKI is synchronized by the rising edge of RSTB.
6.3 Functional Timing
Figure 6-2 is a typical application of the DSP1611/17/18/27/28/29 connected to an external instruction/coefficient
memory and an external data memory. The two external memories share the address bus and data bus. The
instruction/coefficient memory is a read-only memory for the DSP and is enabled by the EROM enable pin. The
data memory is a read/write memory controlled by the ERAMLO enable and the RWN pin. The flexibility of the
wait-states in the DSP allows a wide range of memory speeds to be used.
5-4161
Figure 6-2. EMI Example
Table 6-14. CKO Options
CKO2 CKO1 CKO0 CKO Output Description
1X CKI 2X CKI
PLL
0 0 0 CKI CKI/2 CKI x M/(2N) Free-running internal chip
clock.
0 0 1 CKI/(1+W
X
+W
Y
) CKI/2(1+W
X
+W
Y
) CKI x (M/(2N))/[1+W
Y
] Wait-stated internal clock.
W
X
= X wait-states.
W
Y
= Y wait-states.
0 1 0 1 1 1 Held high.
0 1 1 0 0 0 Held low.
1 0 0 CKI CKI CKI
†
† CKO = CKI even if the PLL is selected as the internal clock source.
Output of CKI buffer
‡
.
‡ For crystal and small-signal clock options only; otherwise, CKO is held low.
1 0 1 X access:
CKI/(1+W
X
)
Y access:
CKI/(1+W
Y
)
X access:
CKI/2(1+W
X
)
Y access:
CKI/2(1+W
Y
)
X access:
CKI x (M/(2N))/[1+W
X
]
Y access:
CKI x (M/(2N))/[1+W
Y
]
Wait-stated internal clock.
W
X
= X wait-states.
W
Y
= Y wait-states.
1 1 0 Undefined Undefined Undefined Reserved
1 1 1 Undefined Undefined Undefined Reserved
W
CS
DATA
MEMORY
DB[15:0]
AB[15:0]
EROM
ERAMLO
RWN
DSP1611/17/18/27/28/29
CS
PROGRAM
MEMORY
OE
16
16
OE