LTC4110
47
4110fb
PCB LAYOUT CONSIDERATIONS
For maximum effi ciency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical fi eld (EMI) radiation and high frequency resonant
problems, proper layout of the components connected to
the IC is essential.
Flyback Layout
Lowest EMI and maximum effi ciency are obtained when the
high frequency switching current loop area is minimized.
It is best to make direct connections, avoiding the use of
other circuit board copper planes, i.e. no vias, in making
the following connections for this prevents current based
noise injection into the copper planes below.
1. Input/output capacitors positive terminals need to
be placed as close as possible between the fl yback
transformer “top” or positive supply rail connections
and R
SNS(FET)
ground connection.
2. Place fl yback MOSFETs drain connections right next
to the fl yback transformers “bottom” connections.
3. Place the R
SNS(FET)
current sense resistor right next
to the N-MOSFET source connections completing
the connection back to the input/output capacitors’
negative terminals.
4. Place the snubber connections as close as possible
to the circuit after the above layout connections are
completed as required. Again, avoid using vias.
5. The layer below the fl yback layout should be ground.
Other Recommendations
6. Optionally use vias to connect power supply sources
positive and negative (ground) connections from
other copper layers to the fl yback layout. Place
multiple vias in a tight cluster such that they act as
one large via. Recommended 1 via for each 0.5A of
current
7. The current sense feedback traces must be routed
together as a single pair on the same layer at any
given time with smallest trace spacing possible.
Locate any fi lter component on these traces next to
the IC and not at the sense resistor location.
8. The control IC must be close to the switching FET’s
gate terminals. Keep the gate drive signals short for
a clean FET drive. This includes IC supply pins that
connect to the switching FET source pins. The IC can
be placed on the opposite side of the PCB relative to
fl yback layout above.
9. Figure 21 shows an inexpensive way to achieve
Kelvin like sensing using standard current sense
resistors.
APPLICATIONS INFORMATION
TO CSP AND CSN
4110 F21
DIRECTION OF CHARGING CURRENT
R
SNS(BAT)
Figure 21. Kelvin Sensing of Battery Current
