LTC4110
41
4110fb
Avoid capacitors with high leakage currents. See the
Programming Charge Time with TIMER and V
REF
Pins
section for details concerning the V
REF
pin. For minimum
delay open the ACPDLY pin.
BAT PIN CURRENT IN IDLE MODE
When LTC4110 is in IDLE mode (i.e., not in charge, calibra-
tion or backup mode), there will be a typical 30μA current
pulled from the battery through the BAT pin, if this current
is of concern, a diode in series with a resistor can be con-
nected between DCIN and battery to compensate it.
SHOW BATTERY FULL WITH ACPB AND CHGB
Tie the source of an N-MOSFET to ACPb, gate to CHGb and
drain in series with R to an LED to show battery full. In
that case if CHG or ACP status LED is not needed, replace
it with a short but keep the pull-up resistor.
This current ramp starts at zero right after the primary side
MOSFET (CHGFET in charge mode, DCHFET in calibration
mode) is turned on. The current rises linearly towards a
peak of V
SEC
/400k (where V
SEC
= BAT in charge mode,
V
SEC
= DCIN in calibration mode), shutting off once the
primary side MOSFET is turned off. A series resistor (R
SL
)
connecting the I
SENSE
pin to the current sense resistor
(R
SNS(FET)
) thus develops a ramping voltage drop. From
the perspective of the I
SENSE
pin, this ramping voltage
adds to the voltage across the sense resistor, effectively
reducing the current comparator threshold in proportion
to duty cycle. This stabilizes the control loop against
subharmonic oscillation. The amount of reduction in the
current comparator threshold (
Δ
V
ISENSE
) can be calculated
using the following equation:
Δ
V
ISENSE
=
DUTY CYCLE •
V
SEC
400k
• R
SL
To program m = m2,
R
N
k R
F Lm
SL
SNS FET
=
1 400
•
•
•
,
where
N = transformer turns ratio N
BAT
/N
DCIN
R
SNS(FET)
= sense resistor connected between MOSFET
and GND
f = switching frequency
Lm = magnetizing inductance of the transformer
Designs not needing slope compensation may replace
R
SL
with a short.
CALCULATING IC POWER DISSIPATION
The power dissipation of the LTC4110 is dependent upon
the gate charge of the two MOSFETs (Q
G1
and Q
G2
). The
gate charge is determined from the manufacturer’s data
sheet and is dependent upon both the gate voltage swing
and the drain voltage swing of the MOSFET. Use 5V for
the gate voltage swing and V
DCIN
for the drain voltage
swing.
P
D
= V
DCIN
• (f
OSC
(Q
G1
+ Q
G2
) + I
Q
)
APPLICATIONS INFORMATION
Figure 18. Display Battery Full
FULL
ACP
+5V
CHG
CHGb
ACPb
4110 F18
FLYBACK COMPENSATION
The values given for the I
TH
pin in the application schematics
have been found to compensate both the voltage loop and
current loop quite well. However, if the resistor connected
to I
CHG
, I
CAL
or I
PCC
is larger than 100k, a 37k resistor in
series with a 100nF capacitor should also be connected
between that pin and GND to compensate the loop.
SLOPE COMPENSATION
The LTC4110 injects a ramping current through its I
SENSE
pin into an external slope compensation resistor (R
SL
).
