LTC4110
27
4110fb
OPERATION
SMBUS INTERFACE
All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is a SMBus
slave device. All internal LTC4110 registers may be updated
and accessed through the SMBus interface as required.
The SMBus protocol is a derivative of the I
2
C-Bus
TM
. (For
a complete description of the bus protocol requirements,
reference “The I
2
C-Bus and How to Use It, V1.0” by Phil-
ips
®
, and “System Management Bus Specifi cation, Version
1.1,” from the SMBus organization). See Table 6: Register
Command Set Description and Table 7: Summary of Sup-
ported SMBus Functions, for complete details.
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condi-
tion, or power-on reset will reset the SMBus interface to
an initial state at any time. The LTC4110 command set is
interpreted by the SMBus interface and passed onto the
charger controller block as control signals or updates to
internal registers. Smart battery charge commands are
Table 5c. GPIO2 Modes
HOST PROGRAMMED BIT SETTINGS
GPIO_2 MODE
DATA
NOTE
GPIO_2_EN
GPIO_2_OUT
GPIO_2_BUFLT
0
0
0
Digital Input
Input Data
GPIO_2_IN
1
X
1
Status Output
BKUP_FLTb
With Pull-Up
1
0
0
Digital Output
0
With Pull-Up
1
1
0
Digital Output
1
With Pull-Up
Table 5d. GPIO2 Power Up Mode (SELA = 0.5 • V
REF
)
FORCED BIT SETTINGS
GPIO_2 MODE
DATA
NOTE
GPIO_2_EN
GPIO_2_OUT
GPIO_2_ BUFLT
1
X
1
Status Output
BKUP_FLTb
With Pull-Up
Table 5e. GPIO3 Modes
HOST PROGRAMMED BIT SETTINGS
GPIO_3 MODE
DATA
NOTE
GPIO_3_EN
GPIO_3_OUT
GPIO_3_CAL
0
0
0
Digital Input
Input Data
GPIO_3_IN
1
X
1
Status Output
CAL_COMPLETEb
With Pull-Up
1
0
0
Digital Output
0
With Pull-Up
1
1
0
Digital Output
1
With Pull-Up
Table 5f. GPIO3 Power Up Mode (SELA = 0.5 • V
REF
)
FORCED BIT SETTINGS
GPIO_3 MODE
DATA
NOTE
GPIO_3_EN
GPIO_3_OUT
GPIO_3_ CAL
1
X
1
Status Output
CHG_FLTb
With Pull-Up