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LGE Internal Use Only
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
LGE Internal Use Only
Figure. 3-4-3
GM200 Memory Circuit
Figure. 3-4-2 DBB EBU SUBSYSTEM BLOCK DIAGRAM
The DBB External Bus Interface provides a memory-mapped interface to external devices such as NOR Flash,
NAND Flash, SRAM, SDRAM, PSRAM, and other custom devices.
The External Memory Interface contains three distinct memory controllers: a NAND Flash Controller (NFC), a
n SDRAM Controller (SDC), and the External Bus Controller (EBC).
These three controllers share the external pins. They also share an arbiter through which the DMA controller
s (via DDBUS, ADBUS, and DMABUS) and the processor cores (via DSPBUS and MCUEBUS) access external de
vices. The following figure shows the external memory interface block diagram.
▣
NOR
512Mbits
A[1:25]
D[0:15]
nWAIT
SD_CS
SD_RAS/SD_CAS
SDCLK/CKE
NOR_CS
nRESET
nRD/nWE/F_DPD
Die #1
Die #1
VMEMOUT
(1.88V, 150mA)
1V88_VMEM
nADV
BURSTCLK
SDRAM 128Mbits
1 Bank
2 Bank
3 Bank
4 Bank
ADD18/ADD19
(Bank Select)
SD_WE/DQM0/DQM1
2^25 X 16bits = 512Mbits
AD6725
SDRAM Controller
External Bus Controller
PF38F5060M0Y0BE
( Numonyx, Bellaire)