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Only for training and service purposes
LGE Internal Use Only
3. TECHNICAL BRIEF
LGE Internal Use Only
3.1.2 Features of AD6725-ATLAS3HLITE
Complete Single-Chip Programmable Digital Baseband Processor with four main
subsystems
MCU Control Processor Subsystem:
32-bit ARM926EJ-S® MCU Control Processor
208 MHz operation at 1.2V
2 dedicated caches, 16kB each, for instructions and data
4kB Instruction Tightly Coupled Memory (TCM)
2-Mbit of on-chip System SRAM
Ciphering co-processor for GPRS supporting GEA1 and GEA2 encryption algorithms
Kasumi cipher coprocessor for GEA3 encryption
Dedicated multi-channel DMA controller
DSP Subsystem:
16-bit fixed-point Blackfin® DSP Processor
208 MHz operation at 1.2V
Memory:
- L1 program space: 64kB SRAM and 16kB configurable as instruction cache or SRAM
- L1 data space: Two banks of 16K bytes, each with 8K bytes of dedicated SRAM and an
additional 8K bytes that can be configured as either cache or SRAM
- L2 space: 64kB SRAM
Ciphering coprocessor (GEA1 and GEA2)
Kasumi cipher coprocessor for GEA3 encryption
Dedicated multi-channel DMA controller
Peripherals Subsystem:
Shared on-chip peripherals and off-chip interfaces
Support for Burst-mode, Page-mode NOR Flash memory
Support for NAND Flash memory
Support for SRAM, PSRAM (cellular RAM), and SDRAM
Full-Speed USB 2.0 Dual-Role Interface with OTG (On-The-Go) Host Mode or Peripheral-only mode
Serial Display Interface
8x8 Keypad Interface
Thumbwheel Interface