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MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION

IC401 (MT1506) : CD-R/RW Analog Signal Processor

Block Diagram

33

RFZC1

AT I P

M C L K

AT F M

W B L C L K

AT F G

A G C 3 C

A G C 2 C

A G C 1 C

A G C O N

S

D

ATA

XLA

T

SCLK

DIG.

R E G .

M P X 1

M P X 2

RRFX

VCON

R R F X

A D B C O

B C O

A D O

I N TA G C O N

D E F E C T

FPDOX

FELP

TELP

MPPO

SPPO

DRCLP

RFRP

M P X 1

M P X O U T 1

10-Bit

A D C

TZC

M P X 2

M P X O U T 2

M P X 1

M C L K

MPX2BHC

MPX2PHC

XRST

A

VDD1

A

VSS1

A

VDD2

A

VSS2

A

VDD3

A

VSS3

A

VDD4

A

VSS4

A

VDD5

A

VSS5

VREF

P / H

&

B / H

M P X 2 B

A U X 1

ASH

BSH

DSH

ESH

CSH

FSH

GSH

HSH

M P X 2

M P X 2 B

A U X 2

DRCMO

ROPCO

RRFXLP

DRCSO

VRDC

VWDC1

VWDC2

VRDCO

VWDC1O

VWDC2O

AUX1

AUX2

A P C

V W D C 2 O

V W D C 1 O

V R D C O

WREF1

VWDC1

VWDC1N

WREF2

VWDC2

VWDC2N

FVREF

FPDO

RREF

VRDC

VRDCN

R F P D S H

W F P D S H

R L D O N

W L D O N

FPDOX

R E C D I N

R R F

R R F X L P

R E C D 1

R R F

R R F X

RECD1_DG1

INTAGCON

RECD1-DG1

R R F

O S T C C

E Q R F

R FA G C C

E Q B I A S

GAINUP

GAINUP

DRCMO

DRCSO

H AV C

I N A

I N F

I N G

I N B

G A I N U P

INE

INH

INC

IND

S E R V S H

W B L S H

A D B C O

A D O

B C O

F E O

M C L K

M P P O

S B A D O

S P P O

S / H

&

M AT R I X

R O P C

FE

DRCMO2

DRCSO2

CE/MPP

TE

SBAD

TEIN

RFZC

TRON

XT

OR

XT

AND

SHPC

RFZC1VC

SHBC

SBADLP

DEFECT

S E R V O

RFZC1

TZC

DEFECT

Data

Slicer

XDEFM

SLPFN

SLPFP

DEFM

R R F

TE

FE

CE/MPP

SBAD

A

VSS

TESTM2

VREF

SBADLP

INA

INB

INC

IND

HA

VC

INA

INB

INC

IND

HA

VC

W R F

R O P C O

R O P C C

H 11 T

A D C T G

INA

INB

INC

IND

HA

VC

WLDON

DEFECT

E Q R F

V C O N

G A I N U P

E Q R F

M C L K

DVDD1

DVSS1

DVDD2

DVSS2

SUBGND

TESTM1

A

TFM

FPDO

ROPCO

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Содержание GCE-8160B

Страница 1: ...ration at each double speed quadruple speed eighth speed 7 Supports CD RW write operation at double speed and quadruple speed 8 PIO Mode 4 Multi DMA Mode 2 9 Multimedia MPC 3 Spec compliant 10 Support CD TEXT read write 5 Audio 1 Output 16 bit digital data over ATA interface 2 8 Times Digital Filter for CD Audio 3 Software Volume Control 4 Equipped with audio line output and headphone jack for aud...

Страница 2: ...t track 4 Emergency Eject Hole Insert a paper clip here to eject the Disc tray manually or when there is no power 5 Volume control This is used to adjust the output volume of the headphone jack It can t be used to adjust the output volume for the audio output connectors on the rear panel NOTE Turn the volume down before turning on the power Sudden loud noises can damage your hearing 6 Headphone ja...

Страница 3: ...on as this could cause a short circuit and damage the system Always turn the power OFF when connecting or disconnecting the cable 3 Jumper Connector This jumper determines whether the drive is configured as a master or slave Changing the master slave configuration takes effect after power on reset 4 Analog Audio Output Connector Provides output to a sound card analog signal Generally you need this...

Страница 4: ...hanged conditions of disc and change in operating temperature Jitter The 16 value of the time variation between leading and trailing edges of a specific I3 I11 pit or land as measured by Time Interval Analysis Deviation The difference between a fixed value of Pit length and Land length TOC Table Of Contents in the Lead in Area the subcode Q channel contains information about the Tracks on the disc...

Страница 5: ...Land Track pitch p Radial Direction Iw A O a a Groove Land Radial Error Signal The Groove wobble Average center Actual center CD ROM CD R CD RW Standard Yellow Book Orange Book II Orange Book III Record Not available Write once Re writable I 11 Itop 0 6 0 6 0 55 M11 0 70 HF Modulation Write Laser Power mW 10 30 mW 6 25 mW Read Laser Power mW 0 5 mW 0 7 mW 1 0 mW Jitter 35 nsec 35 nsec 35 nsec Refl...

Страница 6: ...n the disc It is so called WORM Write Once Read Many CD It is composed of polycarbonate layer Organic dye layer Reflective layer and Protective layer Gold Silver Reflective layer is used to enhance the reflectivity According to the kinds of Organic dye layer it is divided by Green CD Gold CD Blue CD Laser Wavelength 780 nm Laser Power read 0 7 mW Recording Power 4x 10 15mW 8x 14 20mW 12x 15 30mW 1...

Страница 7: ...iting and reading is enabled by the difference of reflectivity It is possible to overwrite about 1000 times Laser Wavelength 780 nm Laser Power Read 1 0mW Recording Power Erase 4 18mW Write 6 35mW When disc rewriting new data is overwritten previously recorded data Polycarbonate layer has a Pre Groove which make a track Lens H D Beam Spot Focusing Lens Laser Spot at Constant Read Intensity Reflect...

Страница 8: ...Spot Recorded Mark Reflected Light Signal Reflected Light Signal Below ORP Mark Too Short At Optimum Record Power ORP Above ORP Mark Too Long Time 6 Writing process of CD RW Disc Write Power Erase Power Read Power Groove Crystal Amorphous Amorphous Recorded state lower reflectivity Melting quenching Heating gradual cooling Crystal phase Erased state higher reflectivity ...

Страница 9: ...Area Lead out Area Center hole Clamping and Label Area Information Area PCA PMA Test Area Count Area Diameter 15 mm Diameter 45 mm Diameter 120 mm Unrecorded Disc Tsl 00 35 65 Tsl 00 15 05 Tsl 00 13 25 Tsl 99 59 74 00 00 00 in out Test Area for performing OPC procedures Count Area to find the usable area immediately in T A Tsl start time of the Lead in Area as encoded in ATIP PMA Program Memory Ar...

Страница 10: ...ad_In area so that general Driver can read it Because PCA and PMA area exist before Lead In area General CD Player or CD ROM Drive can t read these areas 9 OPC and ROPC 1 OPC Optimum Power Control This is the first step of writing process because CD writer has its own laser power value and media have different writing characteristics This is determined by the Writing characteristic speed temperatu...

Страница 11: ...Reference B level value c Normalization of B level is used to eliminate the effect of reflectivity fluctuation The reflected B level value is normalized by the disc reflectivity itself 24 C CD D R R R RW W Media Write Strategy Determination PCA Test Area Program Area PMA Area Lead In Area Lead out Area OPC PCA Count Area ROPC Recording Capacity of CD R RW 74Minute Recording media 2048 Byte Sector ...

Страница 12: ...2 Axis Actuator IC1 PDIC IC2 FPDIC C1 C2 GND G D C E RF GND H A B F Vc GND GND GND Vcc Vc Bin OUT PDIN VOUT VCC VREF VCC GND IOUT IINR IOUT IIN2 GND IIN3 GND RFREQ RAMP GND ENABLE GND OSCEN WEN3 VCC WEN2 GND GND 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 6 5 4 3 2 1 FCS TRK TRK FCS GND PDGND F B A H PDVCC PDVC G D C E RF SUM FPDVCC FPDVC FPDGND FPDO VCC VCC VRDC VWD...

Страница 13: ... Method A D B C k x F H E G This signal is generated in RF IC IC401 MT1506 and controls the pick up s left and right shift to find to track on Disc 3 RF Signal A B C D This signal is converted to DATA signal in DSP IC IC301 MT1505 26 Pick Up module Photo Diode Tracking Focusing Infrared Iaser k F H E G A D B C A D B C k F H E G Offset TE Tp Sub2 Main Tp 2 Sub1 Track Center F E D C A B H G ...

Страница 14: ...9 21 21 26 24 28 RFPDSH WFPDSH IC201 MT1501 WLDON 10K 4 7K 73 72 19 20 29 20 28 27 26 25 24 23 22 21 54 53 M1 M1 FPDO M2 M2 M2 VWDC10 M2 M2 M2 M2 D RREF V WDC1G W1DAC WDAC1G 10 10 RWMODE WREF1ON Level Shift to GND Level Shift to GND S H S H S H WDAC2 WDAC1 VRDC VRDCN FPDO VRDC RREF VWDC1N VWDC1 WREF1 VWDC2N VWDC2 WREF2 VWDC1 VRDCG VRDCG VRDCG x1 x2 x1 x2 x2 x4 x8 x10 FPDOG VRDCDAG VWDC2G WAPC2ON W...

Страница 15: ... power control for CD R RW disc The first APC loop amplifies up to 10x the FMD signal FPDO to enhance the accuracy of read power control VRDCG is used to adjust the gain of FMD signal The built in 8 bit RDAC is used to set the read power level The 2nd 3rd APC loop is used for high power control Both WDAC1 and WDAC2 are 10 bats DAC which are used to set the wanted power level The 3rd APC loop can a...

Страница 16: ...302B IC201 MT1501 Offset adj 9 8 15 14 16 7 13 10 95 10 122 96 97 98 2 3 4 5 LPF LPF ADD MPPG LPF LPF GAIN ADD LPF x1 x1 x2 ADD x1 x3 Offset adj EQRF Filter VGA Offset adj Data Slicer Offset adj Offset adj HPF AGC1 2 Gain Adj Gain Adj Gain Adj Gain Adj Gain Fix Gain Fix CE MPP CEI 11 121 TE TEI 12 120 SBAD SBAD 14 118 EQRF RFIS RFI 88 123 124 ATFG ATFM ATFG 60 50 41 LPF 40K 80K 160K 320KHz LPF LPF...

Страница 17: ...ocus Error Detector Track Error Detector A B C D E F G H IC401 MT1506 FE TE TE FE A D PARALLEL DIGITAL COMPENSATOR DAC SLED COMPENSATOR STEP1 STEP2 IC301 Servo Control MT1505 Tracking x5 Focus x5 Tracking Focusing Actuator FEO TEO F F T T Sled Control M Stepping Control Logic SL1 IC501 M63024FP SL1 SL2 SL2 IC501 M63024FP 27 115 28 114 108 107 1 2 ...

Страница 18: ... aim of Tracking Servo is to make laser beam trace the data track on disc Tracking Error TE signal is generated from tracking error detection block in MT1506 IC401 using DPP Differential Push Pull Method DPP method uses not only main beam A B C D but side beams E F and G H for correcting DC offset generated in Push Pull method The remaining procedures of TE signal processing in MT1505 is similar t...

Страница 19: ...x CAV CD ROM Recorded area in CD R Spindle Servo is controlled by IC201 MT1501 IC301 MT1505 and servo signal is output via WDMO IC201 pin74 32 C B D A E F G H Pick up IC401 MT1506 Wobble Signal Generator RF SRF ATFG Data PLL Spindle Control PWM EQRF CD EFM CLV CAV x40 Hall Sensor M Spindle Motor IC301 MT1505 IC201 MT1501 IC501 M63024F 6 8 IC510 BA6664FM WDMO RDMO FG Divider Wobble Spindle CLV Cont...

Страница 20: ...I Data Laser Power Ref IC203 AT93C86 2KB EEPROM IC302 39SF020A 256KB Flash ROM IC401 MT1506E RF Amp Wobble ALPC DAC IC301 MT1505E DSP Servo Audio 34 57MHz IC201 MT1501E DECODER ENCODER ATIP Demodulator Write Strategy Write S H Singnal I F Data IC202 2MB SDRAM H O S T 5V 12V I F Cable Audio Mute Circuit L R Line Out Audio L R IC501 M63024FP 5Ch Servo DRIVE 3 3V Reset BLOCK DIAGRAM FUNCTIONAL BLOCK ...

Страница 21: ...O VWDC2O AUX1 AUX2 APC VWDC2O VWDC1O VRDCO WREF1 VWDC1 VWDC1N WREF2 VWDC2 VWDC2N FVREF FPDO RREF VRDC VRDCN RFPDSH WFPDSH RLDON WLDON FPDOX RECDIN RRF RRFXLP RECD1 RRF RRFX RECD1_DG1 INTAGCON RECD1 DG1 RRF OSTCC EQRF RFAGCC EQBIAS GAINUP GAINUP DRCMO DRCSO HAVC INA INF ING INB GAINUP INE INH INC IND SERVSH WBLSH ADBCO ADO BCO FEO MCLK MPPO SBADO SPPO S H MATRIX ROPC FE DRCMO2 DRCSO2 CE MPP TE SBAD...

Страница 22: ...Detection Circuit 61 XTOR Digital Output TTL Output of Out of Track Detection Signal OR 62 XTAND Digital Output TTL Output of Out of Track Detection Signal AND 15 SBADLP Analog Input Input of SBAD Signal after LPF for DEFECT Detection 77 DEFECT Digital Output TTL Output of DEFECT Signal 16 SHPC Analog Output External Capacitor Connection for Peak Hold of RFRP Signal 17 RFZC1VC Analog Output Refere...

Страница 23: ...se Output of Laser Diode Controlling in Write APC 1 33 VWDC1O Analog Output Output Voltage of Laser Diode Controlling in Write APC 1 21 WREF2 Analog I O 1 Input of Power Setting Voltage for Write APC 2 2 Output of Write APC 2 Reference Voltage Generated by Built in DAC 23 VWDC2N Analog Input Vin of Midcourse Amplifier for Write APC 2 22 VWDC2 Analog Output Midcourse Output of Laser Diode Controlli...

Страница 24: ...D2 Analog Power Power Pin for Internal Analog Circuitry 5V 31 AVSS2 Analog Ground Ground Pin for Internal Analog Circuitry 43 AVDD3 Analog Power Power Pin for Internal Analog Circuitry 5V 45 AVSS3 Analog Ground Ground Pin for Internal Analog Circuitry 87 AVDD4 Analog Power Power Pin for Internal Analog Circuitry 5V 85 AVSS4 Analog Ground Ground Pin for Internal Analog Circuitry 89 AVDD5 Analog Pow...

Страница 25: ...LL System clock synthesizer IPLLVSS IPLLVDD TEST_MODE PRST FLAG_ 8 0 UA 6 0 MISC Interface Logic 9 URST UINT0 UINT1 UWR URD UALE UA7 UPSEN IO3 UA15 UA14 UA8 UA10 FLASH_WE IO4 FLASH_OE IO5 8 UAD 7 0 DQML BA1 BA0 CKE CLK 12 RA 11 0 RAS ROE RWE CASH RWEH CAS 16 RD 15 0 ADGO ASDATA ALRCK ABCK ACLK DEVSEL DASP CS3FX CS1FX HA 2 0 PDIAG IOCS16 INTRQ DMACK IORDY DIOR DIOW DMARQ HD 15 0 HRST 3 16 XTALO XTA...

Страница 26: ...is used for receiving the digital data after CIRC correction of DSP 208 BCK TTL Input SMT 50K pull up Bit clock input The signal clocks the serial data on the SDATA input Proper synchronization between LRCK and BCK is necessary Audio Output Interface 9 ABCK TTL Output Audio bit clock output The signal clocks the serial data on the ASDATA output Data on the ASDATA signal shall be latched by an audi...

Страница 27: ...ignal main beam side beam Alternate function Alternate function Alternate function Recording Write gate enable signal 33 DECEFM TTL Input SMT 1 Slicing EFM signal input 35 MCLK CMOS Output Slew rate RF main clock output 34 5744M Hz 36 MIRR RFZC TTL Input SMT RF mirror signal input 37 RC IO6 TTL I O Slew rate 50K pull down RF radial contrast signal input Alternate function Programmable bi direction...

Страница 28: ...ADC reference ladder top 64 65 ADCVDD1 ADCVDD2 Analog Power 5V Power pin for ADC circuitry 60 67 ADCVSS1 ADCVSS2 Analog Ground Ground pin for ADC circuitry Reference Voltage Interface 68 BGVSS Analog Ground Ground pin for reference voltage generation circuitry 69 VREFO Analog output 2V reference voltage output 70 V2REFO Analog output 4V reference voltage output 71 BGVDD Analog Power 5V Power pin f...

Страница 29: ... used for 8 bit data transfers Normally data transfers are 16 bit wide Note All pins except HD7 no any pull may be selectively pull up or pull down with 20K resistant 114 DMARQ TTL Output DMA request This signal is used for DMA data transfers between host and device and it shall be asserted by the MT1501 when it is ready to transfer data to or from the host The direction of data transfer is contro...

Страница 30: ...to Device 0 that it has completed diagnostics 126 123 125 HA2 HA0 HA1 TTL Input SMT 50K pull up Device Address This is the 3 bit binary coded address provided by the host to access an ATA register or data 128 CS1FX TTL Input SMT 50K pull up Device Chip Select 0 for 1Fxh 17xh This is the chip select signal from the host to select the Command Block Registers 129 CS3FX TTL Input SMT 50K pull up Devic...

Страница 31: ...SDRAM application this pin is Chip Select signal output connected to CS pin of SDRAM When two 2 bank SDRAM are used this pin musts connect to CS pin of first SDRAM 168 CASH RWEH 3 3V CMOS Output Slew rate PDR Column Address Strobe High RAM Write Enable High When a 16 bit DRAM is used this active low pin functions as Column address Strobe High for accessing the upper bytes of a two CAS RAM or as Wr...

Страница 32: ...ddress bus bit 15 and14 input Alternate function Address bus bit 15 and 14 output during IDE flash programming mode 199 FLASH_WE IO4 TTL I O Slew rate 50K pull up Flash memory write enable signal output low active Alternate function Programmable bi directional IO4 For non flash ROM application the pin can be programmed as GPIO function 201 202 204 UA8 UA9 UA10 TTL I O Slew rate 50K pull up Address...

Страница 33: ...0 90 DSEFM O5 89 UP1_7 MUTE 88 UP1_6 GSW 87 UP1_5 CB 86 UP1_4 APCSW 85 UP1_3 84 UP1_2 AKXRST 83 UP1_1 82 PLAY_ 81 EJECT_ 80 UP3_5 UT0 79 UP3_4 UT0 78 UP3_1 UTXD 77 UP3_0 URXD 76 DGND 75 UXI O4 74 DVDD5 73 UA7 OI5 72 UA6 OI4 71 UA5 OI3 70 UA4 OI2 69 UA3 OI1 68 IA2 OI1 67 UA1 O9 66 UA0 O8 65 64 DACVDD LO 63 DACVREF 62 RO 61 DACVSS 60 VPVSS 59 VCOCIN 58 VPVDD 57 UP3_7 URD_ 56 UP3_6 UWR_ 55 DVDD3 54 U...

Страница 34: ...input High Audio serial data input 17 ALRCK TTL input High Audio serial LR input 19 ABCK TTL input High Audio serial bit clock input 20 EXCK TTL I O output 4mA Subcode data clock This clock is used for reading writing subcode data out through SBSO pin Default is output 21 SBSY TTL output 4mA Subcode block sync signal This pin is high when S0 and S1 is detected 22 WFCK TTL output 4mA Frame sync sig...

Страница 35: ...Lower address data bus output for external device 38 UALE TTL I O 50K pull_up 4mA Address latch enable output active high Alternate function Programmable GPIO 37 UPSEN_ TTL I O 50K pull_up 4mA Programmable store enable output active low PSEN_ enables the external ROM output port Alternate function Programmable output 36 UP1_0 UA16 TTL I O Slew rate 50K pull_up 4mA Programmable bi directional I O A...

Страница 36: ...RAYOUT_ TTL pull up input Tray_is_out input A logical low indicates the tray is out Feedback flag from tray connector 101 LIMIT_ TTL pull up input Sledge inner limit input active low 103 TROPEN PWM TTL output Tray open output Controlled by µP 104 TRCLOSE PWM TTL output Tray close output Controlled by µP Motor and Actuator Driver Interface 106 FG TTL Input SMT 50K pull up Motor Hall sensor input 10...

Страница 37: ...log Input RF signal input 125 ADCVSS Ground Ground pin for ADC circuitry 126 RFDTSLV Analog Output RF data slicer level output 127 SCO Analog Output Analog slicer current output 128 ADCVDD Analog Power 5V Power pin for ADC circuitry 1 RFRO Analog Output RF ripple detect output 2 RFRPSLV Analog Output RF ripple slice level output 3 HRFZC Analog Input High frequency RF ripple zero crossing 4 RFBIAS ...

Страница 38: ...mp Direction comp Direction comp Direction comp BIAS Brake select TSD Current comp Current comp Current comp FG x3 VM1 RSP U V W RSL1 SL1 SL1 VM2 RSL2 SL2 SL2 MU1 MU2 OCS 5VCC LOIN VM3 LO LO FO FO GND TO TO TOIN FOIN SL2IN SL1IN REF SPIN HW HW HV HV HU HU FG s s s s Frequency generator 5V power supply Regulator Reg x5 Tracking x5 Focus x8 VM1 ...

Страница 39: ...Motor Power Supply1 for Spindle 23 HB Bias for Hall Sensor 24 FG Frequency generator output 25 REF Reference voltage input 26 SPIN Spindle control voltage input 27 FOIN Focus control voltage input 28 TOIN Tracking control voltage input 29 GND GND 30 TO Tracking inverted output 31 TO Tracking non inverted output 32 5VCC 5V Power Supply for FS TS 33 GND GND 34 FO Focus non inverted output 35 FO Focu...

Страница 40: ...cuit Board A Remove the Cabinet in the direction of arrow 4 See Fig 1 3 B Release 2 hooks a and remove the CD Tray drawing forward C Remove the Main Circuit Board in the direction of arrow 5 D At this time be careful not to damage the 4 connectors are positioned at bottom or right side of the Main Circuit Board 2 MECHANISM ASSY DISASSEMBLY 2 1 Pick up Unit A Release screw B B Separate the Pick up ...

Страница 41: ...2 2 Pick up A Release 1 screw C and remove the Pick up Pick up Unit Pick up C C Fig 2 2 9 ...

Страница 42: ...B A 007 A02 A01 020 028 029 030 400 032 400 021 020 050 413 413 413 001 413 430 012 009 008 013 014 005 035 016 015 004 006 A B C D E F G H 1 2 3 4 5 017 003 002 010 011 400 400 030 031 027 026 034 025 430 419 021 400 11 12 EXPLODED VIEW ...

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