Lattice Semiconductor LatticeSC PCI Express x1, Руководство пользователя

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LatticeSC PCI Express x1
Lattice Semiconductor Evaluation Board User’s Guide
SERDES Channels
SMA Connections
(see Appendix A, Figure 5)
DC coupled top-mounted SMA connectors connect to the two SERDES TX and RX channels. These pins are
directly coupled to the designated SMA connector creating a path for both input and output differential data.
Table 9. SERDES Connectors (see Appendix A, Figure 8)
SERDES SFP Transceiver Interface
(see Appendix A, Figure 8 )
A small form-factor pluggable (SFP) transceiver cage is included for evaluation of SFP specific protocols. The PCB
includes the appropriate power and high-speed circuitry needed for the SFP standard transceiver.
Table 10. SFP Connections to SERDES Pins (see Appendix A, Figure 5)
Table 11. SFP Control and Status Connections to FPGA
SERDES SATA Channels
(see Appendix A, Figure 8 )
AC-coupled connections are included to attach SATA type cables to SERDES channels for board-to-board or loop-
back purposes. The connectors are configured using the 7-pin SATA specifications.
SMA Channel Name
900-Ball
fpBGA SMA Channel Name
900-Ball
fpBGA
J13 A_HDI N P1_LEFT B6 J10 A_HDOUTP1_LEFT A6
J15 A_HDI NN 1_LEFT B5 J12 A_HDOUT N 1_LEFT A5
J9 A_HDI N P2_LEFT B7 J14 A_HDOUTP2_LEFT A7
J11 A_HDI NN 2_LEFT B 8 J16 A_HDOUT N 2_LEFT A 8
SFP RX Channel Name
900-Ball
fpBGA SFP TX Channel Name
900-Ball
fpBGA
RD+ A_HDI N P0_RIGHT B2 8 TD+ A_HDOUTP0_RIGHT A2 8
RD- A_HDI NN 0_RIGHT B27 TD- A_HDOUT N 0_RIGHT A27
SFP Pin
900-Ball
fpBGA SFP Pin
900-Ball
fpBGA
TxFault A15 ModeDef0 E15
TxDis C13 ModeDef1 D15
LOS G15 ModeDef3 C14
RateSel F15