13
LatticeSC PCI Express x1
Lattice Semiconductor
Evaluation Board User’s Guide
RS-232 Interface
J36
(see Appendix A, Figures 5 and 16)
A simple 2x5 Header provides a connection to create a RS-232 serial communications port. The connection
includes the proper level shift needed to connect to a serial port of a PC. The RX and TX pins are connected to the
FPGA.
Table 18. RS-232 TX/RX
LCD Interface
J41
(see Appendix A, Figures 5 and 16)
A 2x
8
Header provides a connection to 16-character x 2 line LCD modules such as Varitronix VDM16265. A ribbon
cable connection will allow attachment to the connector. The board includes two variable resistors for LCD adjust-
ments. VR1 adjusts the backlight and VR2 provides contrast adjustment. A user design must be included in the
FPGA to drive this feature.
I
2
C Interface
(see Appendix A, Figures 5 and 16)
I
2
C interface is supplied between the FPGA and two ICs. This interface is used to access a Maxim temperature
sensing device as well as a EEPROM. The temperature-sensing device is also connected back to the FPGA via the
PTEMP pins to monitor device temperature.
Table 19. I
2
C Interface
Ethernet Interface
(see Appendix A, Figures 5 and 13)
Interconnection to Base 10/100/1000 Ethernet protocols is supported via a RJ-45 connection (J35). This connec-
tion is electrically interfaced to the FPGA through a tri-speed PHY device. Use of this interface requires a MAC
27
LA_10
AK6
2
8
LA_26
AJ13
29
LA_11
AK7
30
LA_27
AD15
31
LA_12
AF14
32
LA_2
8
AE15
33
LA_13
AF15
34
LA_29
AK12
35
LA_14
AJ11
36
LA_30
AK13
37
LA_15
AG13
3
8
LA_31
AJ14
Si
g
nal
900-Ball fpBGA
Buffer Type
RS232-RXD
F13
LVCMOS25
RS232-TXD
F12
LVCMOS25
Si
g
nal
900-Ball fpBGA
Buffer Type
SCL
B11
LVCMOS25 or LVTTL33
SDA
B12
LVCMOS25 or LVTTL33
Table 17. Logic Analyzer Connections (Continued)
MICTOR Pin
Si
g
nal
900-Ball fpBGA
MICTOR Pin
Si
g
nal
900-Ball fpBGA
