Lattice Semiconductor LatticeSC PCI Express x1, Руководство пользователя

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LatticeSC PCI Express x1
Lattice Semiconductor Evaluation Board User’s Guide
RLDRAM-II Memory Interface
(see Appendix A, Figures 14 and 15)
Interconnection to a Micron MT49H16M1 8 CFM-25 SDRAM memory device is supplied on board. It includes the
proper termination and interface requirements needed to operate at speed.
Table 22. LatticeSC FPGA to On-board SDRAM Connections
A_7 P27 Q_7 AH2 8 D_7 AK1 8
A_ 8 N 29 Q_ 8 AJ2 8 D_ 8 AK19
A_9 N 2 8 Q_9 AE22 D_9 AH17
A_10 R25 Q_10 AK29 D_10 AH1 8
A_11 R2 8 Q_11 AK2 8 D_11 AG17
A_12 N 27 Q_12 AH21 D_12 AJ1 8
A_13 L30 Q_13 AH23 D_13 AJ19
A_14 J30 Q_14 AH22 D_14 AK20
A_15 M26 Q_15 AG22 D_15 AK21
A_16 G29 Q_16 AG21 D_16 AF1 8
A_17 F29 Q_17 AF21 D_17 AG1 8
R_ N AA30
W _ N Y30
CQ AK24
K AJ20
K_ N AJ21
NetName
900 Ball
fpBGA NetName
900 Ball
fpBGA NetName
900 Ball
fpBGA NetName
900 Ball
fpBGA
A_0 AH4 D_0 V2 Q_0 V1 BA_0 AJ2
A_1 AG5 D_1 W 2 Q_1 U5 BA_1 AK2
A_2 AF 8 D_2 V5 Q_2 U4 BA_2 AD7
A_3 AG 8 D_3 V4 Q_3 T4 CS_ N AH1
A_4 AH3 D_4 Y1 Q_4 T5 DM AJ12
A_5 AJ3 D_5 AA1 Q_5 U1 QK AC7
A_6 AF9 D_6 Y2 Q_6 T1 QVLD N 3
A_7 AE10 D_7 AA2 Q_7 V3 DK AC4
A_ 8 AK3 D_ 8 Y3 Q_ 8 U3 DK_ N AD4
A_9 AJ4 D_9 W 3 Q_9 T6 CK AC3
A_10 AE11 D_10 AB1 Q_10 U2 CK_ N AD3
A_11 AF10 D_11 AC1 Q_11 T2
A_12 AH7 D_12 W 5 Q_12 R4
A_13 AH 8 D_13 Y5 Q_13 R1
A_14 AE12 D_14 Y6 Q_14 P1
A_15 AE13 D_15 AD2 Q_15 R2
A_16 AK4 D_16 AE2 Q_16 P4
A_17 AK5 D_17 AB5 Q_17 P3
Table 21. QDR2 Memory Interface Pinouts (Continued)
NetName FPGA Ball NetName FPGA Ball NetName FPGA Ball