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LatticeSC PCI Express x1
Lattice Semiconductor
Evaluation Board User’s Guide
Introduction
This user’s guide describes the LatticeSC PCI Express x1 Evaluation Board featuring the LatticeSC LFSCM3GA25
device in a 900 fpBGA package. The stand-alone evaluation PCB provides a functional platform for development
and rapid prototyping of applications that require high-speed SERDES interfaces to PCI Express protocols.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias. The
nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete evaluation of the LatticeSC device. This
user’s guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the Lat-
ticeSC FPGA.
Figure 1. LatticeSC PCI Express x1 Evaluation Board
Features
• Four SERDES high-speed channels interfaced to SMA test points and clock connections SERDES interface to
x1 PCI Express edge fingers
• RJ-45 interface for Ethernet
• QDR2 and RLDRAMII memory devices
• SFP Transceiver cage and associated interface
• SATA-like connections to SERDES channels
• Power connections and power sources
• ispVM
®
programming support
• On-board and external reference clock sources
– Interchangeable clock oscillators
– On-board reference clock management
• ORCAstra Demonstration Software interface via standard ispVM JTAG connection
