9
LatticeSC PCI Express x1
Lattice Semiconductor
Evaluation Board User’s Guide
Table 5. Clock Source Selection (see Appendix A, Figures 5 and 10)
W
hen using FPGA control, 3.3V VCCIO must be used in bank 1. Refer to Bank1 VCCIO section of this document.
Table 6. Clock Input SMA (see Appendix A, Figure 10)
The clocks sources are fanned-out across the board to several destinations. These clocks are all differential and
must be used accordingly. These include SERDES reference clocks, PLL, and primary clock inputs.
Table 7. Clock Distribution (see Appendix A, Figure 11)
The clocks are also driven to SMA connections for driving off-board.
Table 8. Clock Output SMAs (see Appendix A, Figure 11)
SERDES Reference Clock
The 50-ohm terminated SMA connectors are provided the supply reference clocks directly to the LatticeSC device
from the clock management device. This device will drive clocks to both SERDES quads via 100-ohm LVDS signal-
ing. On-board clock oscillators mentioned in the previous sections can be chosen to drive the same SERDES refer-
ence clocks. Also the board can be provisioned to source the clock from the PCI Express edge-fingers directly to
FPGA input pins.
Both of these input clock sources are routed through clock management devices allowing for clock source selection
from a SMA input connector. This is accomplished by using the MUX selector driven by the FPGA output.
BGA-A19 BGA-A20
Clock Source
Clock Source
L
L
Oscillator
SMA
L
H
SMA
Oscillator
H
H
Oscillator
Oscillator
H
L
Oscillator
SMA
Pin is low when open/float.
SMA
Si
g
nal
J29
SMA Ref Input to Left Quad
J30
SMA Reference - Input to Left Quad
J33
SMA Ref Input to Right Quad
J34
SMA Reference - Input to Right Quad
Clock Net
BGA
Clock Destination
FPGA_REFCLKP_L
P
8
PCLKT7_2
FPGA_REFCLK
N
_L
R
8
PCLKC7_2
FPGA_REFCLKP_R
AD26
LRC_PLLB_T
FPGA_REFCLK
N
_R
AC25
LRC_PLLB_C
A_REFCLKP_L
B1
SERDES[360]
A_REFCLK
N
_L
C1
SERDES[360]
A_REFCLKP_R
B30
SERDES[3e0]
A_REFCLK
N
_R
C30
SERDES[3e0]
Net Name
SMA
SMA
EXTCLOCK_L
J31
J32
EXTCLOCK_R
J33
J34
