6
ECP5-5G Versa Development Board
Table 4. JTAG Chain Selector
J50 Shunts
JTAG Chain
1-2, 3-4, 5-6
ECP5-5G + ispClock
1-2, 3-5
ECP5-5G only
2-4, 5-6
ispClock only
Figure 5. J50 Settings
ECP5-5G +
ispCLOCK
ECP5-5G
only
ispCLOCK
only
Figure 6. ECP5-5G Status LEDs and Push-button Controls
The LEDs indicate the configuration status of the ECP5-5G FPGA.
•
D17 (red)
illuminated indicates that programming was aborted or reinitialized, driving the INITN output low.
•
D20 (green)
illuminated indicates the successful completion of configuration by releasing the open collector
DONE output pin.
•
D19 (red)
illuminated indicates that PROGRAMN is low.
•
D18 (red)
illuminated indicates that GSRN is low.
