5
ECP5-5G Versa Development Board
Setting the Configuration Mode
The ECP5-5G device on the ECP5-5G Versa Development Board supports a variety of configuration modes,
including 1149.1 JTAG and Master SPI. Refer to TN1260,
ECP5 and ECP5-5G sysCONFIG Usage Guide
. On the
PCB, use the CFG Setting Dip Switch SW4 described in Table 3.
Note: SW4.4 is unused.
Figure 3. SW4
Table 3.
Configuration Mode
CFG[2:0]
SW4.3
SW4.2
SW4.1
1149.1 JTAG only
000
Down
Down
Down
Slave SPI
001
Down
Down
Up
Master SPI
010
Down
Up
Down
SCM (Slave_Serial)
101
Up
Down
Up
SCM (Slave_Parallel)
111
Up
Up
Up
CFG[2:0] Selection
Board Programming
The ECP5-5G programmable devices can be programmed using a computer running Lattice Diamond or Lattice
Diamond Programmer software connected to the Development board via a standard mini-USB cable. Refer to the
ECP5-5G Versa Development Kit Quick Start Guide (QS039) for more details. Once the programming software is
installed and the USB cable is connected to the board, the programmable devices can be programmed.
Figure 4. J50
The ECP5-5G FPGA (U1) and the ispClock5406D (U13) device can be programmed individually or together. JTAG
Chain Selector Header J50 is used to select which device(s) will be connected to the JTAG programming bus. The
ECP5-5G FPGA SRAM can be programmed directly, or the subtended configuration serial SPI flash (U52) pro-
grammed, via the same J50 setting. See Table 4 and the diagrams below.
