Lattice Semiconductor ECP5-5G, Руководство пользователя

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18
ECP5-5G Versa Development Board
Appendix A. Schematics
Figure 13. Board Block Design
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
Power Device Power Pins
Programming 3.3V SPI
PCSA
Bank 8
ECP5
Bank 0
Bank 3
FPGA
Bank 6 Bank 7
Bank 1
Bank 2
SERDES
Designator U1 is the FPGA DUT.
PCIe X1 CH#0
CLK5406
REFERENCE
CLOCKS
PCIe RefClk 156.25M OSC
Expansion Port- 3.3V
1.5V 16-Bit DDR3
PCSA RefClk General Clk
2.5V RGMII PHY#1 2.5V RGMII PHY#2
Expansion Port-3.3V
SMA Test CH#3
Expansion Clk
PLL
100.00M DIFF OSC
LED SEGMENT ARRAY
USER DIP SWITCH
USER LEDS
Revision History: Sept 25, 2015 Rev A Final Design SH
Bank 2
Bank 6,7
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Lattice Semicond
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10
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Board Bloc
k
Diagram
ECP5-5G
V
ERSA E
v
al Boar
d
A
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ednesday, Septem
b
e
r 23,
2015
Da
te
:
Size
S
c
hematic Re
v
of
Sheet
Title
Lattice Semicond
u
ctor Applications
Email: te
c
h
s
u
p
p
o
rt@Latti
c
e
s
e
m
i.c
o
m
Boar
d
R
e
v
P
roject
B
A
10
1
Board Bloc
k
Diagram
ECP5-5G
V
ERSA E
v
al Boar
d
A
W
ednesday, Septem
b
e
r 23,
2015