Lattice Semiconductor ECP5-5G, Руководство пользователя

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21
ECP5-5G Versa Development Board
Figure 16. SERDES
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
X1 PCIe Board Fingers
All Nets to SMAs are 100-ohm differential pairs. The P and N traces shall be <20mil matched in length
All Nets are 85-ohm differential pairs. The P and N traces shall be <20mil matched in length
B side = Primary Component Side(TOP) A side = Secondary Component Side(BOTTOM)
Schematic symbols rev 4.1
SERDES
PHY 1 &
2
SGMI
I
SMA SMA
x
1
_PERp0
x
1
_PERn0
PR
S
N
T3#
PC
IE
_
3
V
3
PR
S
N
T1#
x
1
_PERp0
x
1
_PERn0
x1_PETp0 x1_PETn0
PC
IE
_
3
V
3
HDRX
N
0_D0CH1
HDRX
P
0
_
D
0CH1
HDT
X
P
0
_
D
0CH1
HDT
X
N
0_D0CH1
P
C
IE
_CLKP
P
C
IE
_CLK
N
PR
S
N
T1#
PR
S
N
T3#
R
E
FCLKP_D0
RE
FCLK
N
_D0
x
1
_PETp0
x
1
_PETn0
HDRX
P
0
_
D
0CH1
HDRX
N
0_D0CH1
HDTX
N
0_D0CH0
HDTX
P
0
_
D
0CH0
HDTX
N
0_D0CH1
HDTX
P
0
_
D
0CH1
HDRX
N
0_D1CH1
HDRX
P
0
_
D
1CH1
HDRX
N
0_D1CH0
HDRX
P
0
_
D
1CH0
HDTX
N
0_D1CH0
HDTX
P
0
_
D
1CH0
HDTX
N
0_D1CH1
HDTX
P
0
_
D
1CH1
R
E
FCLKP_D1
RE
FCLK
N
_D1
12_0
V
I
N
V
CCHTX0
3_3
V
V
CCA
0
V
CCHTX0
V
CCA
0
V
CCHTX1
V
CCA
1
V
CCHTX1
V
CCA
1
PC
IE
_
C
L
K
P
[9
]
PC
IE
_
C
L
K
N
[9
]
PC
IE
_PERST
N
[3
]
PR
S
N
T[
9
]
R
E
FCLKP_D0
[9
]
RE
FCLK
N
_D0
[9]
HDT
X
P
0
_
D
1CH0
[5
]
HDT
X
N
0_D1CH0
[5
]
HDT
X
P
0
_
D
1CH1
[6
]
HDT
X
N
0_D1CH1
[6
]
HDRX
P
0
_
D
1CH0
[5
]
HDRX
N
0_D1CH0
[5
]
HDRX
P
0
_
D
1CH1
[6
]
HDRX
N
0_D1CH1
[6
]
R
E
FCLKP_D1
[9
]
RE
FCLK
N
_D1
[9]
Da
te
:
Size
S
c
hematic Re
v
of
Sheet
Title
Lattice Semicond
u
ctor Applications
Email: te
c
h
s
u
p
p
o
rt@Latti
c
e
s
e
m
i.c
o
m
Boar
d
R
e
v
P
roject
B
A
10
SERDES
ECP5-5G
V
ERSA E
v
al Boar
d
A
W
ednesday
, Septem
b
e
r 23,
2015
4
Da
te
:
Size
S
c
hematic Re
v
of
Sheet
Title
Lattice Semicond
u
ctor Applications
Email: te
c
h
s
u
p
p
o
rt@Latti
c
e
s
e
m
i.c
o
m
Boar
d
R
e
v
P
roject
B
A
10
SERDES
ECP5-5G
V
ERSA E
v
al Boar
d
A
W
ednesday
, Septem
b
e
r 23,
2015
4
Da
te
:
Size
S
c
hematic Re
v
of
Sheet
Title
Lattice Semicond
u
ctor Applications
Email: te
c
h
s
u
p
p
o
rt@Latti
c
e
s
e
m
i.c
o
m
Boar
d
R
e
v
P
roject
B
A
10
SERDES
ECP5-5G
V
ERSA E
v
al Boar
d
A
W
ednesday
, Septem
b
e
r 23,
2015
4
J5 SMA
1
2 3 4 5
R72
4_7K-0603SMT
C92
10 N F-0402SMT
C
8
9
10 N F-0402SMT
C91
100 N F-0402SMT
C90
1 N F-0402SMT
C111
100 N F-0402SMT
C
N
1
P
C
I
Express x1 Edge Finger Conn
.
PRS
N
T1#
A1
+12
V
A2
+12
V
A3
G
N
D
A4
JT
AG2
A5
JT
AG3
A6
JT
AG4
A7
JT
AG5
A
8
+3.3
V
A9
+3.3
V
A1
0
PERST
#
A1
1
G
N
D
A1
2
REFCLK
+
A1
3
REFCLK
-
A1
4
G
N
D
A1
5
PERp0
A1
6
PERn0
A1
7
G
N
D
A1
8
+12
V
B1
+12
V
B2
RS
V
D_B
3
B3
G
N
D
B4
SMCLK
B5
SMDAT
B6
G
N
D
B7
+3.3
V
B
8
JT
AG1
B9
3.3
V
a
u
x
B10
W
AKE#
B11
RS
V
D_B12
B12
G
N
D
B13
PETp0
B14
PETn0
B15
G
N
D
B16
PRS
N
T3#
B17
G
N
D
B1
8
LFE5UM-45F-BG3
8
1
U1H V
CCHTX0_D0CH0
T7
V
CCHTX0_D1CH0
T11
V
CCHTX1_D0CH1
T10
V
CCHTX1_D1CH1
T14
V
CCHRX0_D0CH0
T
8
V
CCHRX0_D1CH0
T12
V
CCHRX1_D0CH1
T9
V
CCHRX1_D1CH1
T13
HDTXP0_D0CH0
W
4
HDTX
N
0_D0CH0
W
5
HDTXP0_D0CH1
W8
HDTX
N
0_D0CH1
W
9
HDTXP0_D1CH1
W
17
HDTX
N
0_D1CH1
W
1
8
HDTXP0_D1CH0
W
13
HDTX
N
0_D1CH0
W
14
REFCLKP_D0
Y11
REFCLK
N
_D0
Y12
HDRXP0_D0CH0
Y5
HDRX
N
0_D0CH0
Y6
HDRXP0_D0CH1
Y7
HDRX
N
0_D0CH1
Y
8
HDRXP0_D1CH0
Y14
HDRX
N
0_D1CH0
Y15
HDRXP0_D1CH1
Y16
HDRX
N
0_D1CH1
Y17
REFCLKP_D1
Y19
REFCLK
N
_D1
W
20
J4
HEADER 3X
2
2 4 6
1 3 5
C113
10 N F-0402SMT
J
8
SMA
1
2 3 4 5
R17
8
OPE
N
-0603SM
T
C
8
7
100
N
FX5R-0402SMT
C105
1 N F-0402SMT
TP6 Testpoint
1
C9
3
1 N F-0402SMT
C
88
100 N F-0402SMT
C112
1 N F-0402SMT
J6 SMA
1
2 3 4 5
J7 SMA
1
2 3 4 5
C110
10 N F-0402SMT
C
8
6
100
N
FX5R-0402SMT
C106
100 N F-0402SMT