Lattice Semiconductor CrossLink LIF-MD6000, Руководство пользователя

Страница: 4 / 38

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal . All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02010-1.4
1. Introduction
This document describes the Lattice Semiconductor CrossLink™ LIF-MD6000 Master Link board that supports a variety
of demos, encompassing different signaling logic standards bridging with MIPI
®
CSI-2/DSI interface. The board‘s key
component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support different bridging
solutions.
For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation
and more, see the Lattice website at:
www.latticesemi.com/masterlink
For details about the CrossLink device, refer to FPGA-DS-02007, CrossLink Family Data Sheet.
The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set
of schematics, and bill of materials for LIF-MD6000 Master Link board.
Refer to Appendix A, B, C, D, E, F for the schematics and BOM of the CrossLink LIF-MD6000 Master Link board and the
schematics and BOMs of the Breakout IO Link and SMA IO Link boards that are included in the demo kit.
Circuits on the development kit board:

Programming Circuit

Mini USB Type-B connector to FTDI

FTDI to CrossLink using SPI

FTDI to XO3LF device using JTAG

CrossLink

MIPI CSI-2/DSI hard block

Bridging of multiple signaling standards

SPI flash configuration

General Purpose Input/Output

LED display

LCMXO3LF-1300E

I
2
C muxing
Figure 1.1 shows the top view of the LIF-MD6000 Master Link board and its key components. Figure 1.2 on the next
page shows the bottom view of the board.
Tx Connector 1 & 2 (U9, U7)
Power Switch (SW1)
External Power Input
External Power Jack (J3)
LCMXO3L-1300E (U19)
USB 2.0 Mini-B (J2)
JTAG Header (J1)
FTDI Chip (U1)
SPI Flash Device (U14)
Rx Connectors (U11, U12)
Power LEDs
LIF-MD6000-CSFBGA81
Debug Header (J18)
Debug and
Configuration LEDs
Reset and wake-up buttons
Switch (SW2)
Clock Source Selection (J26, J27)
Bank 1, 2 Voltage Selection
Headers (J24, J25)
External Clock SMA Inputs
XO3 Reset (SW3)
Figure 1.1. Top View of Master Link Board and its Key Components