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CrossLink LIF-MD6000 Master Link Board 

 

 

Evaluation Board User Guide 
 

© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 

www.latticesemi.com/legal

.  

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 

22 

 

FPGA-EB-02010-1.4 

MIPI Block – MIPI Tx 

5

5

4

4

3

3

2

2

1

1

D

D

C

C

B

B

A

A

T

X

 

C

o

n

n

e

c

t

o

r

1

T

X

 

C

o

n

n

e

c

t

o

r

2

Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms

Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Place MIPI TX resistor network as close to bank 0 as possible.
Trace match *HS*  P & N channels as well as individual pairs.
Minimize routing and trace match *LP* signals to banks 5 and 0.

Piggyback Configuration info:

1.. 0.001uF and 0.1uF is added as the piggyback c

100nF and 470pF is loaded near DUT and 0.001uF and 0.1uF is made piggy back for the following reference designer

C42,C44,C46,C171,C172

CH4_DCK_TX_P
CH4_DCK_TX_N

CH4_DATA0_TX_P
CH4_DATA0_TX_N

CH4_DATA1_TX_P
CH4_DATA1_TX_N

RESETN

SDA
SCL

GPIO1
GPIO2

RESETN

SDA
SCL

GPIO1
GPIO2

CH4_DATA3_TX_P
CH4_DATA3_TX_N

CH4_DATA2_TX_P
CH4_DATA2_TX_N

CSSPIN
MCLK

CH5_DATA3_TX_P
CH5_DATA3_TX_N

CH5_DATA2_TX_P
CH5_DATA2_TX_N

CH5_DCK_TX_P
CH5_DCK_TX_N

CH5_DATA0_TX_P
CH5_DATA0_TX_N

CH5_DATA1_TX_P
CH5_DATA1_TX_N

CSSPIN
MCLK

CH5_DCK_TX_P
CH5_DCK_TX_N
CH5_DATA0_TX_P
CH5_DATA0_TX_N
CH5_DATA1_TX_P
CH5_DATA1_TX_N
CH5_DATA2_TX_P
CH5_DATA2_TX_N
CH5_DATA3_TX_P
CH5_DATA3_TX_N

CH4_DCK_TX_P
CH4_DCK_TX_N
CH4_DATA0_TX_P
CH4_DATA0_TX_N
CH4_DATA1_TX_P
CH4_DATA1_TX_N
CH4_DATA2_TX_P
CH4_DATA2_TX_N
CH4_DATA3_TX_P
CH4_DATA3_TX_N

5V +3.3V +1.8V

5V +3.3V +1.8V

12V

12V

12V

5V

+3.3V

+1.8V

12V

5V

+3.3V

+1.8V

VCC_DPHY

VCC_DPHY

VCC_DPHY

2,5,6

CSSPIN

2,5,6

MCLK

RESETN

5

SDA

6,7

SCL

6,7

SISPI

2,5,6

SPISO

2,5,6

RPI1

5

RPI2

5

XO3_SCL

7

XO3_SDA

7

D

D

Da

a

attte

e

e:::

S

S

Siiizzze

e

e

S

S

Sccch

h

he

e

em

m

ma

a

atttiiiccc   R

R

Re

e

evvv

o

o

offf

S

S

Sh

h

he

e

ee

e

ettt

T

T

Tiiitttllle

e

e

L

L

La

a

attttttiiiccce

e

e   S

S

Se

e

em

m

miiiccco

o

on

n

nd

d

du

u

ucccttto

o

orrr   A

A

Ap

p

pp

p

pllliiiccca

a

atttiiio

o

on

n

nsss

E

E

Em

m

ma

a

aiiilll:::   ttte

e

eccch

h

hsssu

u

up

p

pp

p

po

o

orrrttt@

@

@L

L

La

a

attttttiiiccce

e

essse

e

em

m

miii...ccco

o

om

m

m

B

B

Bo

o

oa

a

arrrd

d

d   R

R

Re

e

evvv

P

P

Prrro

o

ojjje

e

ecccttt

1

1

16

6

6---F

F

FE

E

EB

B

B---1

1

16

6

6

B

B

B

1

1

1...0

0

0

8

8

8

4

4

4

M

M

MiiiP

P

Piii   B

B

Blllo

o

occckkk   ---   M

M

MIIIP

P

PIII   T

T

TX

X

X

L

L

LIIIF

F

FM

M

MD

D

D---6

6

60

0

00

0

00

0

0---6

6

6M

M

MG

G

G8

8

81

1

1III   S

S

Sn

n

no

o

ow

w

w   b

b

brrriiid

d

dg

g

giiin

n

ng

g

g   ssso

o

olllu

u

utttiiio

o

on

n

n

B

B

B

C44

0.01uF
16V

R53

0

R455

0

R453

0

C155

0.1uF

R465

0

R456

0

R454

0

C171

470pF
16V

C156

0.1uF

U7

Hirose - FX12 - 40 Pos

CH4_DCK_P

1

CH4_DCK_N

2

GND

3

CH4_DATA0_P

4

CH4_DATA0_N

5

GND

6

CH4_DATA1_P

7

CH4_DATA1_N

8

GND

9

SN

10

SCLK

11

GND

12

CH4_DATA2_P

13

CH4_DATA2_N

14

GND

15

CH4_DATA3_P

16

CH4_DATA3_N

17

GND

18

12V

19

12V

20

TBD

21

RESETN

22

PWR_5-0V

23

GND

24

GND

25

PWR_3-3V

26

GND

27

GND

28

PWR_1-8V

29

MOSI

30

MISO

31

PWR_1-8V

32

GND

33

GND

34

PWR_3-3V

35

GND

36

GND

37

PWR_5-0V

38

SDA

39

SCL

40

Shield1

41

Shield2

42

Shield3

43

Shield4

44

Shield5

45

Shield6

46

C42

0.01uF
16V

LIFMD6000-csfBGA81

U8D

DPHY1_DP2

C1

DPHY1_DN2

C2

DPHY1_DP0

B1

DPHY1_DN0

B2

DPHY1_CKP

A1

DPHY1_CKN

A2

DPHY1_DP1

A3

DPHY1_DN1

B3

DPHY1_DP3

A4

DPHY1_DN3

B4

DPHY0_DP2

B6

DPHY0_DN2

A6

DPHY0_DP0

B7

DPHY0_DN0

A7

DPHY0_CKP

A8

DPHY0_CKN

A9

DPHY0_DP1

B8

DPHY0_DN1

B9

DPHY0_DP3

C8

DPHY0_DN3

C9

VCCA_DPHY0

D7

VCCA_DPHY1

D3

VCCPLL_DPHY0

C4
C6

VCCPLL_DPHY1

GNDA_DPHY0

C7

GNDA_DPHY1

C3

GNDPLL_DPHYX

B5

VCCA_DPHY1

A5

C159

0.1uF

C41

1uF
4V

C172

470pF
16V

R466

0

R420

0

C46

470pF
16V

C158

0.1uF

R421

0

C160

0.1uF

C45

1uF
16V

R418

0

DNI

U9

Hirose - FX12 - 40 Pos

CH5_DCK_P

1

CH5_DCK_N

2

GND

3

CH5_DATA0_P

4

CH5_DATA0_N

5

GND

6

CH5_DATA1_P

7

CH5_DATA1_N

8

GND

9

SN

10

SCLK

11

GND

12

CH5_DATA2_P

13

CH5_DATA2_N

14

GND

15

CH5_DATA3_P

16

CH5_DATA3_N

17

GND

18

12V

19

12V

20

TBD

21

RESETN

22

PWR_5-0V

23

GND

24

GND

25

PWR_3-3V

26

GND

27

GND

28

PWR_1-8V

29

MOSI

30

MISO

31

PWR_1-8V

32

GND

33

GND

34

PWR_3-3V

35

GND

36

GND

37

PWR_5-0V

38

SDA

39

SCL

40

Shield1

41

Shield2

42

Shield3

43

Shield4

44

Shield5

45

Shield6

46

C161

0.1uF

R481

0

DNI

R51

0

C43

1uF
4V

C162

0.1uF

R482

0

DNI

C157

0.1uF

R52

0

R419

0

DNI

C178

0.1uF
16V

Содержание CrossLink LIF-MD6000

Страница 1: ...CrossLink LIF MD6000 Master Link Board Evaluation Board User Guide FPGA EB 02010 Version 1 4 April 2018...

Страница 2: ...erials 27 Appendix C SMA IOL EVN BRD Schematics 33 Appendix D SMA IOL EVN BRD Bill of Materials 34 Appendix E B IOL EVN BRD Schematics 35 Appendix F B IOL EVN BRD Bill of Materials 36 RevisionHistory...

Страница 3: ...tive holders The specifications and information herein are subject to change without notice FPGA EB 02010 1 4 3 Acronyms in This Document A list of acronyms used in this document Acronym Definition CM...

Страница 4: ...ons of on board jumper settings programming circuit a complete set of schematics and bill of materials for LIF MD6000 Master Link board Refer to Appendix A B C D E F for the schematics and BOM of the...

Страница 5: ...istered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifica...

Страница 6: ...OFF SHORT ON J4 External clock input for MIPI D PHY reference clock J6 External or internal clock selection 1 2 External 2 3 Internal J18 External SP I2C access SW2 Configuration reset for LIF MD6000...

Страница 7: ...ks with Diamond programmer software to provide interfaces for JTAG to program MachXO2 1300E SPI to program both CrossLink and SPI Flash Memory USB Mini B J2 FTDI Chip U1 SPI Flash U14 LIF MD6000 CSFBG...

Страница 8: ...HY I F D PHY Rx LVDS CMOS D PHY Rx LVDS CMOS Tx Connector 2 Tx Connector 1 D PHY I F Figure 3 2 Bridging Block 3 2 I2 C Expander Figure 3 3 shows the block diagram of the I2 C expander The LCMXO3LF 12...

Страница 9: ...XO3LF 1300E as well as to the external boards connected to Tx and Rx Headers Each I O and core voltage rail on the board is accessible by a test point on the board The current flowing to each rail can...

Страница 10: ...n herein are subject to change without notice 10 FPGA EB 02010 1 4 Table 4 2 Device Power Rail Summary and Test Points Voltage Rail Source Rail Current Sense Resistor Test Points 12 V 12_Ext 12V 5 V 1...

Страница 11: ...their respective holders The specifications and information herein are subject to change without notice FPGA EB 02010 1 4 11 5 Status Indicators The LED status indicators on the board show power confi...

Страница 12: ...or DATA1_TX_P Pin 7 J6 SMA connector for DATA1_TX_N Pin 8 J7 SMA connector for DATA2_TX_P Pin 13 J8 SMA connector for DATA2_TX_N Pin 14 J9 SMA connector for DATA3_TX_P Pin 16 J10 SMA connector for DAT...

Страница 13: ...tents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information...

Страница 14: ...s signals to the 26 pin header J2 Table 7 1 Headers and Test Connectors Part Description Setting J2 13x2 Header U1 Connector to interface to CrossLink Master Link board Table 7 2 U1 Connector Descript...

Страница 15: ...change without notice FPGA EB 02010 1 4 15 Table 7 3 J2 Header Description Pin Name Mapping to U1 1 3 3V N A 2 1 8V N A 3 RESETN Pin 22 4 CH4_DCK_TX_P Pin 1 5 SDA Pin 39 6 CH4_DCK_TX_N Pin 2 7 SCL Pin...

Страница 16: ...and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information here...

Страница 17: ...s of their respective holders The specifications and information herein are subject to change without notice FPGA EB 02010 1 4 17 8 Ordering Information Table 8 1 Ordering Information Description Orde...

Страница 18: ...legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice 18 FPGA EB 02...

Страница 19: ...I2C LVDS RX In LVDS RX In SPI BANK 3 4 BANK 2 BANK 0 LCMXO3LF 1300 MG121 JTAG I2C 3 I O Expander I2C Switch Targeted FPGA SPI FLASH I2C SPI SPI I2C 2 I2C 1 SPI SPI I2C D D Da a at t te e e S S Siiiz...

Страница 20: ...B B 1 1 1 0 0 0 8 8 8 2 2 2 F F FT T TD D DI I I I I IN N NT T TE E ER R RF F FA A AC C CE E E L L LI I IF F FM M MD D D 6 6 60 0 00 0 00 0 0 6 6 6M M MG G G8 8 81 1 1I I I S S Sn n no o ow w w b b b...

Страница 21: ...c c ce e es s se e em m miii c c co o om m m B B Bo o oa a ar r rd d d R R Re e ev v v P P Pr r ro o ojjje e ec c ct t t 1 1 16 6 6 F F FE E EB B B 1 1 16 6 6 B B B 1 1 1 0 0 0 8 8 8 3 3 3 P P PO O OW...

Страница 22: ...t t t T T Tiiit t tllle e e L L La a at t tt t tiiic c ce e e S S Se e em m miiic c co o on n nd d du u uc c ct t to o or r r A A Ap p pp p pllliiic c ca a at t tiiio o on n ns s s E E Em m ma a aiiil...

Страница 23: ...o o of f f S S Sh h he e ee e et t t T T Tiiit t tllle e e L L La a at t tt t tiiic c ce e e S S Se e em m miiic c co o on n nd d du u uc c ct t to o or r r A A Ap p pp p pllliiic c ca a at t tiiio o...

Страница 24: ...Tiiit t tllle e e L L La a at t tt t tiiic c ce e e S S Se e em m miiic c co o on n nd d du u uc c ct t to o or r r A A Ap p pp p pllliiic c ca a at t tiiio o on n ns s s E E Em m ma a aiiilll t t te...

Страница 25: ...uF C104 0 1uF C151 0 1uF R404 4 7k R436 680R C105 0 1uF R440 4 7k C141 10uF D23 Red 1 2 R437 680R R405 4 7k SW3 SYS_RST C106 1uF R179 650 D30 blue 1 2 BANK2 LCMXO3LF 1200E MG121 U19C VCCIO2 H6 H7 H9 J...

Страница 26: ...y MIPI LVDS Simulation Requirement 1 MIPI Differential Mode insertion Loss shall be 1 6dB at 750 MHz 2 MIPI Differential Mode Return Loss shall be 15dB at 750 MHz 3 MIPI Common Mode Return Loss shall...

Страница 27: ...NC Samsung Cap Ceramic 0 1 F 10 V X5R 20 SMD 0402 85C Paper T R 7 C41 C43 C53 C60 C67 C71 6 1 F C0306 LLR185C70G1 05ME05L Murata CAP CER 1 F 4 V X7S 0306 8 C42 C44 2 0 01 F C0201 GRM033R61C 103KA12D M...

Страница 28: ...3 GRM188R71E 104KA01D Murata CAP CER 0 1 F 25 V 10 X7R 0603 27 C127 1 680 pF C0603 C0603C681J3 GACTU Kemet CAP CER 680 pF 25 V 5 NP0 0603 28 C128 1 0 47 F C0402 CL05A474KA5 NNNC Samsung CAP CER 0 47 F...

Страница 29: ...1 Molex CONN HEADER 8POS 100 VERT TIN 42 J2 1 SKT_MINI USB_B_R A skt_miniu sb_b_ra 5075BMR 05 SM CR Neltron CONN MINI USB RCPT RA TYPE B SMD 43 J3 1 PJ 032A PJ 032A PJ 032A CUI Inc CON PWR JCK 2 0 X 6...

Страница 30: ...47 23 0 R0603 RC0603JR 070RL Yageo Res 1 10 W 0 0 5 0603 58 R9 R10 2 2K2 R0603 CRCW06032 K20FKEA Vishay RES SMD 2 2 k 1 1 10 W 0603 59 R11 R17 2 12K R0603 RC0603FR 0712KL Yageo RES SMD 12 k 1 1 10 W 0...

Страница 31: ...R117 R119 R121 10 100 R0402 DNI RC0402FR 07100RL Yageo RES SMD 100 1 1 16 W 0402 74 R160 R432 2 100K R0402 RMCF0402JT 100K Stackpole Electronics Inc RES 100 k 1 16 W 5 0402 75 R166 R441 R442 R443 R444...

Страница 32: ...17ST 33T3G sot223_4p NCP1117ST33T3G On Semi IC Reg LDO 3 3 V SOT 223 92 U6 1 NCP1117ST 25T3G sot223_4p NCP1117ST25T3G On Semi IC Reg LDO 2 5 V SOT 223 93 U7 U9 U11 U12 4 Hirose FX12 40 Pos Hirose FX12...

Страница 33: ...or r r A A Ap p pp p pllliiic c ca a at t tiiio o on n ns s s E E Em m ma a aiiilll t t te e ec c ch h hs s su u up p pp p po o or r rt t t L L La a at t tt t tiiic c ce e es s se e em m miii c c co...

Страница 34: ...turer Description 1 GND1 5 V 1 8 V 3 3 V SN SDA SCLK SCL RESETN MOSI MISO GND 12 TP_S_ 40_63 tp_s_40_ 63 DNI Square test point 40 mil inner diameter 63 mil outer diameter 2 C1 C4 2 1 F C0402 C0402C105...

Страница 35: ...ate Size Schematic Rev of Sheet Title Lattice Semiconductor Applications Email techsupport Latticesemi com Board Rev Project 04 May 15 B 1 0 1 1 100MILS_DEBUG HEADER LCMXO3L 4300 MG256 MIPI Briding so...

Страница 36: ...Quantity Part PCB Footprint Comments Part_ Number Manufacturer Description 1 GND1 5 V 1 8 V 3 3 V SN SCLK MOSI MISO GND 9 TP_S_40_ 63 tp_s_40_63 DNL Square test point 40 mil inner diameter 63 mil out...

Страница 37: ...e Version Change Summary April 2018 1 4 Made schematics searchable March 2018 1 3 Added footnote to Table 2 1 September 2017 1 2 Changed document number from EB105 to FPGA EB 02010 Changed J25 from VC...

Страница 38: ...7th Floor 111 SW 5th Avenue Portland OR 97204 USA T 503 268 8000 www latticesemi com...

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