CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4
23
CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
Bank 1, 2 – LVDS Rx
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U8
LVDS RX TERMINATION RESISTORS
R
X
C
o
n
n
e
c
t
o
r
1
R
X
C
o
n
n
e
c
t
o
r
2
Note : Speed of the bus, < 2.5ps skew for pairs and
across the bus, traces should be 100 Ohms
Trace match LVDSI* pins between P and N channels as
well as individual pairs. Minimize routing and trace
match *CD* signals to bank 3 pins.
Note :
1) Match length within pair as well as other pairs with +/- 5% tolerence
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
All the power rails should be capable of carrying 1A current
3)
1. 0.001uF and 1.5nF is added as the piggyback cap
100nF and 1.5nF is loaded near DUT and 0.001uF and 1.5nF is
made piggy back for the following reference designer
C51,C59
DNI
Piggyback Configuration info:
NOTE : PLACE SWITCH IN THE TOP SIDE
EXTERNAL RESET
Default short (J29.2,J29.3)
CSSPIN
MCLK
CH0_DCK_P
CH0_DCK_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA2_P
CH0_DATA2_N
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
GPIO3
GPIO4
GPIO3
GPIO4
CSSPIN
MCLK
CH1_DCK_P
CH1_DCK_N
CH1_DATA0_P
CH1_DATA0_N
CH1_DATA2_P
CH1_DATA2_N
CH1_DATA1_P
CH1_DATA1_N
CH1_DATA3_P
CH1_DATA3_N
RESETN
CMOS_IO_7
CMOS_IO_8
CMOS_IO_1
CMOS_IO_1
CMOS_IO_2
CMOS_IO_3
CMOS_IO_4
CMOS_IO_7
CMOS_IO_8
CMOS_IO_2
CMOS_IO_1
CMOS_IO_3
CMOS_IO_4
CMOS_IO_5
CMOS_IO_6
CMOS_IO_1
CMOS_IO_2
GPIO3
GPIO4
CH0_DATA2_P
CH0_DATA2_N
CH0_DCK_N
CH0_DCK_P
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA0_P
CH0_DATA0_N
CH0_DATA1_P
CH0_DATA1_N
CH0_DATA3_P
CH0_DATA3_N
CH1_DATA0_P
CH1_DATA0_N
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA2_P
CH1_DATA2_N
CH1_DATA1_P
CH1_DATA1_N
CH1_DATA0_N
CH1_DATA0_P
CH1_DATA3_P
CH1_DATA3_N
CH1_DATA2_P
CH1_DATA2_N
CH1_DCK_P
CH1_DCK_N
CH0_DATA2_P
CH0_DATA2_N
CH1_DATA1_P
CH1_DATA1_N
CMOS_IO_3
CH0_DCK_P
CH0_DCK_N
CMOS_IO_2
EXT_RST
CH1_DCK_P
CH1_DCK_N
CMOS_IO_5
CMOS_IO_6
CMOS_IO_4
RESETN
EXT_RST
CMOS_IO_5
CMOS_IO_6
CMOS_IO_7
CMOS_IO_8
5V
+3.3V +1.8V
5V
+3.3V +1.8V
12V
12V
12V
12V
12V
5V
+3.3V
+1.8V
12V
5V
+3.3V
+1.8V
VCCIO1
VCCIO2
VCCIO2
VCCIO1
VCCIO2
VCCIO0
SDA2
7
SCL2
7
2,4,6
CSSPIN
2,4,6
MCLK
RESE
R
T
E
N
SETN
4
7
SCL4
7
SDA4
SDA1
7
SCL1
7
7
SCL3
7
SDA3
SISPI
2,4,6
SPISO
2,4,6
RPI1
4
RPI2
4
D
D
Da
a
attte
e
e:::
S
S
Siiizzze
e
e
S
S
Sccch
h
he
e
em
m
ma
a
atttiiiccc R
R
Re
e
evvv
o
o
offf
S
S
Sh
h
he
e
ee
e
ettt
T
T
Tiiitttllle
e
e
L
L
La
a
attttttiiiccce
e
e S
S
Se
e
em
m
miiiccco
o
on
n
nd
d
du
u
ucccttto
o
orrr A
A
Ap
p
pp
p
pllliiiccca
a
atttiiio
o
on
n
nsss
E
E
Em
m
ma
a
aiiilll::: ttte
e
eccch
h
hsssu
u
up
p
pp
p
po
o
orrrttt@
@
@L
L
La
a
attttttiiiccce
e
essse
e
em
m
miii...ccco
o
om
m
m
B
B
Bo
o
oa
a
arrrd
d
d R
R
Re
e
evvv
P
P
Prrro
o
ojjje
e
ecccttt
1
1
16
6
6---F
F
FE
E
EB
B
B---1
1
16
6
6
B
B
B
1
1
1...0
0
0
8
8
8
5
5
5
B
B
BA
A
AN
N
NK
K
K1
1
1,,,2
2
2 --- L
L
LV
V
VD
D
DS
S
S R
R
RX
X
X
L
L
LIIIF
F
FM
M
MD
D
D---6
6
60
0
00
0
00
0
0---6
6
6M
M
MG
G
G8
8
81
1
1III S
S
Sn
n
no
o
ow
w
w b
b
brrriiid
d
dg
g
giiin
n
ng
g
g ssso
o
olllu
u
utttiiio
o
on
n
n
B
B
B
D8
blue
1
2
R458
0
R55
680R
NI
SW4
EXT
_RST
R424
0
R446
0
C60
1uF
4V
D9
blue
1
2
J29
CON3
1
2
3
R445
4.7k
R461
0
R425
0
R110
100
DNI
C167
0.1uF
C163
0.1uF
C58
100nF
16V
R469
0
J28
CON6
1
2
3
4
5
6
U11
Hirose - FX12 - 40 Pos
CH1_DCK_P
1
CH1_DCK_N
2
GND
3
CH1_DATA0_P
4
CH1_DATA0_N
5
GND
6
CH1_DATA2_P
7
CH1_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12_0V
12
SDA1
13
SCL1
14
GND
15
CH3_DATA0_P
16
CH3_DATA0_N
17
GND
18
CH3_DCK_P
19
CH3_DCK_N
20
PWR_12V
21
RESETN
22
PWR_5-0V
23
CH1_DATA1_P
24
CH1_DATA1_N
25
PWR_3-3V
26
CH1_DATA3_P
27
CH1_DATA3_N
28
PWR_1-8V
29
MOSI
30
MISO
31
PWR_1-8V
32
GND
33
GND
34
PWR_3-3V
35
CH3_DATA1_P
36
CH3_DATA1_N
37
PWR_5-0V
38
SDA
39
SCL
40
Shield1
41
Shield2
42
Shield3
43
Shield4
44
Shield5
45
Shield6
46
R472
0
R462
0
D6
blue
1
2
R113
100
DNI
R111
100
DNI
R470
0
D7
blue
1
2
R476
0
R114
100
DNI
R473
0
R60
0
C164
0.1uF
R117
100
DNI
R459
0
C168
0.1uF
R61
0
R119
100
DNI
C165
0.1uF
C169
0.1uF
R474
0
R467
0
R460
0
C52
6800pF
10V
C166
0.1uF
C170
0.1uF
LIFMD6000-csfBGA81
U8B
PB29A/PCLKT1_0
G7
PB29C/PCLKT1_1
PB29B/PCLKC1_0
J6
G6
PB29D/PCLKC1_1
H6
PB34A/GR_PCLK1_0
D1
PB34C/MIPI_CLKT1_0
PB34B
J5
D2
H5
PB34D/MIPI_CLKC1_0
PB38A
E1
PB38C
PB38B
J4
E2
PB38D
H4
PB43C
J3
PB43D
H3
VCCIO1
F3
VCCIO1
G4
R121
100
DNI
R106
100
DNI
R422
0
DNI
C53
1uF
4V
R450
0
DNI
U12
Hirose - FX12 - 40 Pos
CH0_DCK_P
1
CH0_DCK_N
2
GND
3
CH0_DATA0_P
4
CH0_DATA0_N
5
GND
6
CH0_DATA2_P
7
CH0_DATA2_N
8
GND
9
SN
10
SCLK
11
PWR_12V
12
SDA1
13
SCL1
14
GND
15
CH2_DATA0_P
16
CH2_DATA0_N
17
GND
18
CH2_DCK_P
19
CH2_DCK_N
20
PWR_12-0V
21
RESETN
22
PWR_5-0V
23
CH0_DATA1_P
24
CH0_DATA1_N
25
PWR_3-3V
26
CH0_DATA3_P
27
CH0_DATA3_N
28
PWR_1-8V
29
MOSI
30
MISO
31
PWR_1-8V
32
GND
33
GND
34
PWR_3-3V
35
CH2_DATA1_P
36
CH2_DATA1_N
37
PWR_5-0V
38
SDA
39
SCL
40
Shield1
41
Shield2
42
Shield3
43
Shield4
44
Shield5
45
Shield6
46
R468
0
R423
0
DNI
R463
0
R56
4.7k
C51
100nF
16V
R107
100
DNI
C181
0.1uF
R5
D
7
680R
DNI
C177
470pF
16V
R457
0
R471
0
R464
0
LIFMD6000-csfBGA81
U8C
PB2A
F9
PB2C/MIPI_CLKT2_0
PB2B
G9
F8
PB2D/MIPI_CLKC2_0
G8
PB6A/GR_PCLK2_0
E9
PB6C
PB6B
H9
E8
PB6D
H8
PB12A/GPLLT2_0
F7
PB12C
PB12B/GPLLC2_0
J9
E7
J8
PB12D
PB16A/PCLKT2_0
D9
D8
PB16B/PCLKC2_0
J7
PB16C/PCLKT2_1
H7
PB16D/PCLKC2_1
VCCIO2
E6
VCCIO2
F6
R59
680R
R54
680R
DNI
C59
1.5nF
10V
R475
0
R108
100
DNI
