Lattice Semiconductor ASC Bridge Board, Руководство пользователя

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ASC Bridge Board
Evaluation Board User Guide
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12 FPGA-EB-02025-2.0
10. J16 Fan 1 Header
This fan connector supports either a 3-wire low-side drive fan or 4-wire fan.
Table 10.1. Fan 1 Header Connection
J16 Pin
Number
Description MachXO3-9400 ECP5-45 FPGA Board
Signal Name
Ball Pad Ball Pad
1 GND –– –– ––
2 PWM Switch to GND
*
G15 PT42D C7 PT11B EXPCON_IO44
3 PWM G15 PT42D C7 PT11B EXPCON_IO44
4 Fan Tachometer G12 PT28A C6 PT11A EXPCON_IO45
5 +5 V –– –– ––
6 +12 V –– –– ––
*Note: J16 pin 2 is buffered and inverted from the signal FAN1_PWM. See Figure A.4 in the Appendix A. Board Schematics section
for additional details.
11. J21 Fan 2 Header
This fan connector supports a 3-wire low-side drive fan. The power pin on this connector is selectable between 5 V and
12 V through jumper J20. Shorting the jumper to the 1-2 location selects the 12 V option. The 5 V option is selected
when the jumper in on the 2-3 location.
Table 11.1. Fan 2 Header Connection
J21 Pin
Number
Description MachXO3-9400 ECP5-45 FPGA Board
Signal Name
Ball Pad Ball Pad
1 PWM Switch to GND
*
G15 PT42D D8 PT13B EXPCON_IO42
2 Fan Power –– –– ––
3 Fan Tachometer F15 PT42C E8 PT13A EXPCON_IO43
*Note: J21 pin 1 is buffered and inverted from the signal FAN2_PWM.
See Figure A.4 in the Appendix A. Board Schematics
section for additional details.
12. J19 Fan 3 Header
This fan connector supports a 3-wire high side drive fan. The power for this fan connector is selectable between 5 V
and 12 V through jumper J17. Shorting the jumper to the 1-2 location selects the 12 V option. The 5 V option is selected
when the jumper in on the 2-3 location. A hold-up capacitor is inserted in parallel with the fan to guarantee proper
under speed detection. The ASC Bridge Board has a set of pre-populated capacitors connected through jumper J18. For
fan PWM frequency less than 10 kHz, connect J18 to the 1-2 location. Connect J18 to the 2-3 location for fan PWM
frequency between 10 kHz to 26.7 kHz. If the fan PWM frequency is greater than 40 kHz, leave J18 unconnected. For
more information about fan control, please refer to TN1278, Temperature Monitoring and Fan Control with Platform
Manager 2.
Table 12.1. Fan 3 Header Connection
J19 Pin
Number
Description MachXO3-9400 ECP5-45 FPGA Board
Signal Name
Ball Pad Ball Pad
1 GND –– –– ––
2 PWM Switch to Power
*
E16 PT40C B8 PT15B EXPCON_IO40
3 Fan Tachometer E13 PT28C C8 PT15A EXPCON_IO41
*Note: J19 pin 2 is buffered from the signal FAN3_PWM. See Figure A.4 in the Appendix A. Board Schematics section for additional
details.