ASC Bridge Board
Evaluation Board User Guide
© 2015-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal
.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
FPGA-EB-02025-2.0
6.
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 3.875 inches by 11.5 inches. Five 0.125 inch plated through holes are provided to
allow installation of plastic or metal spacers to lift the board off the desktop to a uniform height.
Operation temperature: 0°C to 55°C
Storage temperature: –40°C to 75°C
Humidity: <95% without condensation
7.
J2 and J3 Female Header
J2 and J3 are 40-pin female headers that connect the signals from either the MachXO3-9400 Development Board or the
ECP5 Versa Development Board to the ASC Bridge Board. The female header carries both signal and power. The
connections for J2 and J3 are listed in
Appendix C
and
Appendix D
.
Note: The connections referenced in this document refer to the LFE5UM-45F-8BG381C device.
8.
J6, J7 and J13 D-SUB25 Connector
The L-ASC10 Evaluation Board is connected to the ASC Bridge Board through D-SUB 25-pin connectors. These
connectors carry both signal and power.
Table 8.1
through
Table 8.3
show the connections between the D-SUB connectors to J2 and J3 connectors.
Table 8.1. J6 D-SUB 25 Connection
J6 Header
Pin Number
ASC Pin Function
Header Connection
Header Pin Number
1
GND
—
—
2
WDAT
J3
13
3
RDAT
J3
9
4
WRCLK
J3
10
5
MANDATORY_RESET
J2
28
6
GND
—
—
7
I2C_WRITE_EN
J2
32
8
ASC_CLK
J3
5
9
3.3 V
—
—
10
N.C.
—
—
11
12 V
—
—
12
5 V
—
—
13
GND
—
—
14
ASC_12V_OC_SHUTDOWN
J3
14
15
ASC_12V_OC_SENSE
J3
12
16
GND
—
—
17
ASC_RESET
J3
7
18
I2C_SCL
J2
18
19
I2C_SDA
J2
16
20
ASC_5V_OC_SHUTDOWN
J3
8
21
ASC_5V_OC_SENSE
J3
6
22
ASC_BOARD_SENSE
J3
4
23
12 V
—
—
24
5 V
—
—
25
5 V
—
—
